Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D technology computer-aided design (TCAD) device simulation data of GAA field-effect transistors (FETs) subjected to both tensile and...

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