An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration
This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers...
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| Veröffentlicht in: | Circuits, systems, and signal processing systems, and signal processing, 2024-07, Vol.43 (7), p.4021-4049 |
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| container_issue | 7 |
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| container_title | Circuits, systems, and signal processing |
| container_volume | 43 |
| creator | Li, Dagang Li, Zehong Chen, Zhuorui Qi, Xiaohu Fan, Hua Zhou, Wei Li, Wei Wang, Ce Cui, Chen Ma, Keyan Feng, Quanyuan Wei, Qi Guo, Xinkai Sun, Yan |
| description | This paper presents a high-resolution 18-bit SAR ADC with a high 10-bit capacitor DAC and a low 8-bit resistor DAC. The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset performance of the comparator. As a result, the design under 180 nm process achieves a signal-to-noise and distortion ratio(SNDR) of 105.5dB and a spurious-free dynamic range (SFDR) of 116.3dB under 1 MS/s sampling rate with a single channel. The effective number of bits (ENOB) can reach 17.23 bits with a Nyquist-rate input while consuming 46 mW from a 5 V supply. The resultant Schreier and Walden figures of merit (FoM) are 178.92 dB and 295.34 fJ/conversion-step, respectively. The proposed SAR ADC occupies an actual area of 3850
μ
m by 2810
μ
m. |
| doi_str_mv | 10.1007/s00034-024-02610-8 |
| format | Article |
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μ
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μ
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μ
m by 2810
μ
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The total required number of the unit capacitors is decreased to 512. Foreground digital calibration based on capacitive recombination is introduced to improve linearity. Preamplifiers and output offset storage(OOS) enhance the noise and offset performance of the comparator. As a result, the design under 180 nm process achieves a signal-to-noise and distortion ratio(SNDR) of 105.5dB and a spurious-free dynamic range (SFDR) of 116.3dB under 1 MS/s sampling rate with a single channel. The effective number of bits (ENOB) can reach 17.23 bits with a Nyquist-rate input while consuming 46 mW from a 5 V supply. The resultant Schreier and Walden figures of merit (FoM) are 178.92 dB and 295.34 fJ/conversion-step, respectively. The proposed SAR ADC occupies an actual area of 3850
μ
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μ
m.</abstract><cop>New York</cop><pub>Springer US</pub><doi>10.1007/s00034-024-02610-8</doi><tpages>29</tpages><orcidid>https://orcid.org/0000-0001-7629-2183</orcidid></addata></record> |
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| subjects | Accuracy Calibration Capacitors Circuits and Systems Electrical Engineering Electronics and Microelectronics Engineering Figure of merit Instrumentation Preamplifiers Science Signal processing Signal,Image and Speech Processing |
| title | An 18-bit SAR ADC with Mixed DAC and Capacitive Recombination Calibration |
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