An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips
This article presents a novel static random access memory computing-in-memory (SRAM-CIM) structure designed for high-precision multiply-and-accumulate (MAC) operations with high energy efficiency (EF), high readout accuracy, and short compute latency. The proposed device employs 1) a time-domain inc...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2024-07, Vol.59 (7), p.2297-2309 |
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| creator | Wu, Ping-Chun Su, Jian-Wei Chung, Yen-Lin Hong, Li-Yang Ren, Jin-Sheng Chang, Fu-Chun Wu, Yuan Chen, Ho-Yu Lin, Chen-Hsun Hsiao, Hsu-Ming Li, Sih-Han Sheu, Shyh-Shyuan Chang, Shih-Chieh Lo, Wei-Chung Wu, Chih-I Lo, Chung-Chuan Liu, Ren-Shuo Hsieh, Chih-Cheng Tang, Kea-Tiong Chang, Meng-Fan |
| description | This article presents a novel static random access memory computing-in-memory (SRAM-CIM) structure designed for high-precision multiply-and-accumulate (MAC) operations with high energy efficiency (EF), high readout accuracy, and short compute latency. The proposed device employs 1) a time-domain incremental-accumulation (TDIA) scheme to enable high-accumulation MAC operations while maintaining a large signal margin across MAC values (MACVs), 2) a dynamic differential-reference (D2REF) scheme based on software-hardware co-design to reduce read energy consumption, and 3) a low-dMACV-aware recursive time-to-digital converter (LMAR-TDC) for implementation with the D2REF scheme to further suppress readout energy consumption. A 28 nm 1 Mb SRAM-CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved EF of 39.31 TOPS/W and compute latency of 6.6 ns for 8b-MAC operations with 64 accumulations per cycle and near-full output precision (22b). |
| doi_str_mv | 10.1109/JSSC.2023.3343669 |
| format | Article |
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The proposed device employs 1) a time-domain incremental-accumulation (TDIA) scheme to enable high-accumulation MAC operations while maintaining a large signal margin across MAC values (MACVs), 2) a dynamic differential-reference (D2REF) scheme based on software-hardware co-design to reduce read energy consumption, and 3) a low-dMACV-aware recursive time-to-digital converter (LMAR-TDC) for implementation with the D2REF scheme to further suppress readout energy consumption. A 28 nm 1 Mb SRAM-CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved EF of 39.31 TOPS/W and compute latency of 6.6 ns for 8b-MAC operations with 64 accumulations per cycle and near-full output precision (22b).</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2023.3343669</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Accumulation ; Artificial intelligence ; Artificial intelligence (AI) ; Co-design ; Computation ; computing-in-memory (CIM) ; Edge AI ; Energy consumption ; In-memory computing ; inference ; Inference mechanisms ; multiply-and-accumulate (MAC) ; SRAM cells ; Static random access memory ; static random access memory (SRAM) ; Time domain analysis</subject><ispartof>IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2297-2309</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c246t-4d33df8086695e43fbf665718d70e7006218e5f90e5ed4b803647573cd41d70a3</cites><orcidid>0000-0002-9689-1236 ; 0000-0003-4070-5059 ; 0000-0002-5311-4955 ; 0000-0001-7566-8185 ; 0000-0001-6905-6350</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10376238$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10376238$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Wu, Ping-Chun</creatorcontrib><creatorcontrib>Su, Jian-Wei</creatorcontrib><creatorcontrib>Chung, Yen-Lin</creatorcontrib><creatorcontrib>Hong, Li-Yang</creatorcontrib><creatorcontrib>Ren, Jin-Sheng</creatorcontrib><creatorcontrib>Chang, Fu-Chun</creatorcontrib><creatorcontrib>Wu, Yuan</creatorcontrib><creatorcontrib>Chen, Ho-Yu</creatorcontrib><creatorcontrib>Lin, Chen-Hsun</creatorcontrib><creatorcontrib>Hsiao, Hsu-Ming</creatorcontrib><creatorcontrib>Li, Sih-Han</creatorcontrib><creatorcontrib>Sheu, Shyh-Shyuan</creatorcontrib><creatorcontrib>Chang, Shih-Chieh</creatorcontrib><creatorcontrib>Lo, Wei-Chung</creatorcontrib><creatorcontrib>Wu, Chih-I</creatorcontrib><creatorcontrib>Lo, Chung-Chuan</creatorcontrib><creatorcontrib>Liu, Ren-Shuo</creatorcontrib><creatorcontrib>Hsieh, Chih-Cheng</creatorcontrib><creatorcontrib>Tang, Kea-Tiong</creatorcontrib><creatorcontrib>Chang, Meng-Fan</creatorcontrib><title>An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This article presents a novel static random access memory computing-in-memory (SRAM-CIM) structure designed for high-precision multiply-and-accumulate (MAC) operations with high energy efficiency (EF), high readout accuracy, and short compute latency. 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A 28 nm 1 Mb SRAM-CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved EF of 39.31 TOPS/W and compute latency of 6.6 ns for 8b-MAC operations with 64 accumulations per cycle and near-full output precision (22b).</description><subject>Accumulation</subject><subject>Artificial intelligence</subject><subject>Artificial intelligence (AI)</subject><subject>Co-design</subject><subject>Computation</subject><subject>computing-in-memory (CIM)</subject><subject>Edge AI</subject><subject>Energy consumption</subject><subject>In-memory computing</subject><subject>inference</subject><subject>Inference mechanisms</subject><subject>multiply-and-accumulate (MAC)</subject><subject>SRAM cells</subject><subject>Static random access memory</subject><subject>static random access memory (SRAM)</subject><subject>Time domain analysis</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkEFLw0AQhRdRsFZ_gOBhwfPW3cxmszmGWLXSotgWvIU0mdQtzabuJof-exPag6dhhvfe8D5C7gWfCMHjp_flMp0EPIAJgASl4gsyEmGomYjg-5KMOBeaxQHn1-TG-12_SqnFiNjEUr1hnw4L401jqVrR5VeyoGlTH7rW2C0zli2wbtyRLvLCNXTt-ytdmRrZc1PnxtKZLRzWaNt8T5Oi6Opun7dDWNU4mszotNwiTX_Mwd-Sqyrfe7w7zzFZv0xX6Rubf7zO0mTOikCqlskSoKw0132RECVUm0qpMBK6jDhGnKtAaAyrmGOIpdxoDkpGYQRFKUUvyWFMHk-5B9f8dujbbNd0zvYvM-ARAA9Vz2pMxEnV1_LeYZUdnKlzd8wEzwas2YA1G7BmZ6y95-HkMYj4Tw-RCkDDH9uxcZY</recordid><startdate>20240701</startdate><enddate>20240701</enddate><creator>Wu, Ping-Chun</creator><creator>Su, Jian-Wei</creator><creator>Chung, Yen-Lin</creator><creator>Hong, Li-Yang</creator><creator>Ren, Jin-Sheng</creator><creator>Chang, Fu-Chun</creator><creator>Wu, Yuan</creator><creator>Chen, Ho-Yu</creator><creator>Lin, Chen-Hsun</creator><creator>Hsiao, Hsu-Ming</creator><creator>Li, Sih-Han</creator><creator>Sheu, Shyh-Shyuan</creator><creator>Chang, Shih-Chieh</creator><creator>Lo, Wei-Chung</creator><creator>Wu, Chih-I</creator><creator>Lo, Chung-Chuan</creator><creator>Liu, Ren-Shuo</creator><creator>Hsieh, Chih-Cheng</creator><creator>Tang, Kea-Tiong</creator><creator>Chang, Meng-Fan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The proposed device employs 1) a time-domain incremental-accumulation (TDIA) scheme to enable high-accumulation MAC operations while maintaining a large signal margin across MAC values (MACVs), 2) a dynamic differential-reference (D2REF) scheme based on software-hardware co-design to reduce read energy consumption, and 3) a low-dMACV-aware recursive time-to-digital converter (LMAR-TDC) for implementation with the D2REF scheme to further suppress readout energy consumption. A 28 nm 1 Mb SRAM-CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved EF of 39.31 TOPS/W and compute latency of 6.6 ns for 8b-MAC operations with 64 accumulations per cycle and near-full output precision (22b).</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2023.3343669</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-9689-1236</orcidid><orcidid>https://orcid.org/0000-0003-4070-5059</orcidid><orcidid>https://orcid.org/0000-0002-5311-4955</orcidid><orcidid>https://orcid.org/0000-0001-7566-8185</orcidid><orcidid>https://orcid.org/0000-0001-6905-6350</orcidid></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2024-07, Vol.59 (7), p.2297-2309 |
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| source | IEEE Electronic Library (IEL) |
| subjects | Accumulation Artificial intelligence Artificial intelligence (AI) Co-design Computation computing-in-memory (CIM) Edge AI Energy consumption In-memory computing inference Inference mechanisms multiply-and-accumulate (MAC) SRAM cells Static random access memory static random access memory (SRAM) Time domain analysis |
| title | An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips |
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