Towards Single-Event Upset detection in Hardware Secure RISC-V processors
Single-event effects and hardware security show close similarities in terms of vulnerabilities and mitigation techniques. Secure processors address physical attacks from the outside, such as external laser stimulation, to compromise the program and extract sensitive information from the systems. To...
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| Veröffentlicht in: | Journal of instrumentation 2024-06, Vol.19 (6), p.C06009 |
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| container_issue | 6 |
| container_start_page | C06009 |
| container_title | Journal of instrumentation |
| container_volume | 19 |
| creator | Jonckers, N. Engelen, B. Appels, K. De Raedemaeker, S. Mariën, L. Prinzie, J. |
| description | Single-event effects and hardware security show close similarities in terms of vulnerabilities and mitigation techniques. Secure processors address physical attacks from the outside, such as external laser stimulation, to compromise the program and extract sensitive information from the systems. To overcome this vulnerability, secure extensions to the hardware architecture are often built into modern processor cores. Given the limited design resources often found in space or high-energy physics experiment development teams, this article addresses the extent to which secure hardware architectures can be a reliable source of processor SEU detection. |
| doi_str_mv | 10.1088/1748-0221/19/06/C06009 |
| format | Article |
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| ispartof | Journal of instrumentation, 2024-06, Vol.19 (6), p.C06009 |
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| language | eng |
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| source | IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link |
| subjects | Computing (architecture, farms, GRID for recording, storage, archiving, and distribution of data) Digital electronic circuits Hardware Microprocessors Radiation-hard electronics RISC Single Event Effects Single event upsets VLSI circuits |
| title | Towards Single-Event Upset detection in Hardware Secure RISC-V processors |
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