Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications

Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employ...

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Veröffentlicht in:	Analog integrated circuits and signal processing 2024-06, Vol.119 (3), p.521-533
Hauptverfasser:	Kalaiselvi, C. M., Sabeenian, R. S.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Arithmetic and logic units Artificial intelligence Artificial neural networks Circuits and Systems Deep learning Electrical Engineering Electronic systems Engineering Field programmable gate arrays Hardware Large scale integration Machine learning Multiplication Multiplication & division Multipliers Neural networks Signal processing Signal,Image and Speech Processing Very large scale integration
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