A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking

A 3-nm FinFET single-port (SP) 6T SRAM macro is proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engaging read cycle time by enhancing the trackability of sense enable ti...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2024-04, Vol.59 (4), p.1225-1234
Hauptverfasser:	Aoyagi, Yumito, Nii, Koji, Yabuuchi, Makoto, Tanaka, Tomotaka, Ishii, Yuichiro, Osada, Yoshiaki, Nakazato, Takaaki, Wang, Isabel, Hsu, Yu-Hao, Cheng, Hong-Chen, Liao, Hung-Jen, Chang, Tsung-Yung Jonathan
Format:	Artikel
Sprache:	eng
Schlagworte:	3 nm bitcell (BC) cache Cache memory Cycle time Delays Density Electric potential far-end pre-charge (FPC) Figure of merit FinFET FinFETs high current (HC) multi-bank Random access memory Resistance single port (SP) SRAM SRAM cells Timing Tracking Voltage weak-bit (WB) tracking
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