Learning-driven Physically-aware Large-scale Circuit Gate Sizing

Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficienc...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:arXiv.org 2024-03
Hauptverfasser: Ye, Yuyang, Xu, Peng, Ren, Lizheng, Chen, Tinghuan, Yan, Hao, Yu, Bei, Shi, Longxing
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title arXiv.org
container_volume
creator Ye, Yuyang
Xu, Peng
Ren, Lizheng
Chen, Tinghuan
Yan, Hao
Yu, Bei
Shi, Longxing
description Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.
format Article
fullrecord <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_journals_2956941863</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2956941863</sourcerecordid><originalsourceid>FETCH-proquest_journals_29569418633</originalsourceid><addsrcrecordid>eNpjYuA0MjY21LUwMTLiYOAtLs4yMDAwMjM3MjU15mRw8ElNLMrLzEvXTSnKLEvNUwjIqCzOTE7MyanUTSxPLEpV8EksSk_VLQYKpSo4ZxYll2aWKLgnlqQqBGdWAfXxMLCmJeYUp_JCaW4GZTfXEGcP3YKi_MLS1OKS-Kz80qI8oFS8kaWpmaWJoYWZsTFxqgAxnTj7</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2956941863</pqid></control><display><type>article</type><title>Learning-driven Physically-aware Large-scale Circuit Gate Sizing</title><source>Free E- Journals</source><creator>Ye, Yuyang ; Xu, Peng ; Ren, Lizheng ; Chen, Tinghuan ; Yan, Hao ; Yu, Bei ; Shi, Longxing</creator><creatorcontrib>Ye, Yuyang ; Xu, Peng ; Ren, Lizheng ; Chen, Tinghuan ; Yan, Hao ; Yu, Bei ; Shi, Longxing</creatorcontrib><description>Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.</description><identifier>EISSN: 2331-8422</identifier><language>eng</language><publisher>Ithaca: Cornell University Library, arXiv.org</publisher><subject>Back propagation ; Design optimization ; Layouts ; Machine learning ; Sizing</subject><ispartof>arXiv.org, 2024-03</ispartof><rights>2024. This work is published under http://arxiv.org/licenses/nonexclusive-distrib/1.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>780,784</link.rule.ids></links><search><creatorcontrib>Ye, Yuyang</creatorcontrib><creatorcontrib>Xu, Peng</creatorcontrib><creatorcontrib>Ren, Lizheng</creatorcontrib><creatorcontrib>Chen, Tinghuan</creatorcontrib><creatorcontrib>Yan, Hao</creatorcontrib><creatorcontrib>Yu, Bei</creatorcontrib><creatorcontrib>Shi, Longxing</creatorcontrib><title>Learning-driven Physically-aware Large-scale Circuit Gate Sizing</title><title>arXiv.org</title><description>Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.</description><subject>Back propagation</subject><subject>Design optimization</subject><subject>Layouts</subject><subject>Machine learning</subject><subject>Sizing</subject><issn>2331-8422</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><recordid>eNpjYuA0MjY21LUwMTLiYOAtLs4yMDAwMjM3MjU15mRw8ElNLMrLzEvXTSnKLEvNUwjIqCzOTE7MyanUTSxPLEpV8EksSk_VLQYKpSo4ZxYll2aWKLgnlqQqBGdWAfXxMLCmJeYUp_JCaW4GZTfXEGcP3YKi_MLS1OKS-Kz80qI8oFS8kaWpmaWJoYWZsTFxqgAxnTj7</recordid><startdate>20240313</startdate><enddate>20240313</enddate><creator>Ye, Yuyang</creator><creator>Xu, Peng</creator><creator>Ren, Lizheng</creator><creator>Chen, Tinghuan</creator><creator>Yan, Hao</creator><creator>Yu, Bei</creator><creator>Shi, Longxing</creator><general>Cornell University Library, arXiv.org</general><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>L6V</scope><scope>M7S</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope></search><sort><creationdate>20240313</creationdate><title>Learning-driven Physically-aware Large-scale Circuit Gate Sizing</title><author>Ye, Yuyang ; Xu, Peng ; Ren, Lizheng ; Chen, Tinghuan ; Yan, Hao ; Yu, Bei ; Shi, Longxing</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-proquest_journals_29569418633</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Back propagation</topic><topic>Design optimization</topic><topic>Layouts</topic><topic>Machine learning</topic><topic>Sizing</topic><toplevel>online_resources</toplevel><creatorcontrib>Ye, Yuyang</creatorcontrib><creatorcontrib>Xu, Peng</creatorcontrib><creatorcontrib>Ren, Lizheng</creatorcontrib><creatorcontrib>Chen, Tinghuan</creatorcontrib><creatorcontrib>Yan, Hao</creatorcontrib><creatorcontrib>Yu, Bei</creatorcontrib><creatorcontrib>Shi, Longxing</creatorcontrib><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science &amp; Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Engineering Collection</collection><collection>Engineering Database</collection><collection>Access via ProQuest (Open Access)</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ye, Yuyang</au><au>Xu, Peng</au><au>Ren, Lizheng</au><au>Chen, Tinghuan</au><au>Yan, Hao</au><au>Yu, Bei</au><au>Shi, Longxing</au><format>book</format><genre>document</genre><ristype>GEN</ristype><atitle>Learning-driven Physically-aware Large-scale Circuit Gate Sizing</atitle><jtitle>arXiv.org</jtitle><date>2024-03-13</date><risdate>2024</risdate><eissn>2331-8422</eissn><abstract>Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.</abstract><cop>Ithaca</cop><pub>Cornell University Library, arXiv.org</pub><oa>free_for_read</oa></addata></record>
fulltext fulltext
identifier EISSN: 2331-8422
ispartof arXiv.org, 2024-03
issn 2331-8422
language eng
recordid cdi_proquest_journals_2956941863
source Free E- Journals
subjects Back propagation
Design optimization
Layouts
Machine learning
Sizing
title Learning-driven Physically-aware Large-scale Circuit Gate Sizing
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T01%3A59%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=document&rft.atitle=Learning-driven%20Physically-aware%20Large-scale%20Circuit%20Gate%20Sizing&rft.jtitle=arXiv.org&rft.au=Ye,%20Yuyang&rft.date=2024-03-13&rft.eissn=2331-8422&rft_id=info:doi/&rft_dat=%3Cproquest%3E2956941863%3C/proquest%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2956941863&rft_id=info:pmid/&rfr_iscdi=true