A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology

In this paper, a four-level pulse amplitude modulation (PAM-4) receiver for single-ended memory interfaces is presented. The frontend signaling path is optimized to maximize the receivers bandwidth in combination with a T-coil that mitigates the loading effect of the electrostatic discharge (ESD) pr...

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Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2024-03, Vol.71 (3), p.1-1
Hauptverfasser:	Sim, Taeyang, Yeom, Sunoh, Im, Hyunwoo, Oh, Youngmin, Seo, Hyeongmin, Ko, Hyeongjun, Chi, Hankyu, Jung, Hae-Kang, Han, Jaeduk
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Bandwidths Bit error rate CMOS Coils CTLE Electrostatic discharges Equalizers Fluctuations Four-level pulse-amplitude modulation (PAM-4) High gain Linearity Pulse amplitude modulation receiver Receivers single-ended T-Coil TAS-TIA Topology Transconductance
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