A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps
This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp...
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| Veröffentlicht in: | SILICON 2021-03, Vol.13 (3), p.787-798 |
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| creator | Das, Debika Chakraborty, Ujjal |
| description | This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp
+
Si
1-x
Ge
x
layer. It offers an ON current of 1.16 × 10
−4
A/μm providing a high ON/OFF ratio of 3.49 × 10
12
and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp
+
Si
1-x
Ge
x
layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (g
m
/I
D
) behaviour. The high ratio of obtained g
m
/I
D
makes it compatible for future low power applications. |
| doi_str_mv | 10.1007/s12633-020-00488-0 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2919361658</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2919361658</sourcerecordid><originalsourceid>FETCH-LOGICAL-c319t-a4be13654d9887363ecd1bd669ee8ecc9f8c5eef437abe6201546b91f9632c0a3</originalsourceid><addsrcrecordid>eNp9kNFKwzAUhoMoOOZewKuA19WkadPkcmzODYYbbIJ3IU1PpbNLZtJe7AF8bzMneue5yQl8_8fhR-iWkntKSPEQaMoZS0hKEkIyIRJygQZUFDyRkorL3528XqNRCDsSh6WF4HKAPsd40_XVETuLp71u8bSBFkznG4PXzrxDh-fQgXe73pquidRmtcDb3lpo8exxi9fga-f32hrA2lZ41jYx5fGzawLgsdXtMTQBNxavPQQ4Ya7GCxudtY6frdeHcIOuat0GGP28Q_QS3ZN5slw9LSbjZWIYlV2isxIo43lWSSEKxhmYipYV5xJAgDGyFiYHqDNW6BJ4Smie8VLSWnKWGqLZEN2dvQfvPnoIndq53scbg0ollYxTnotIpWfKeBeCh1odfLPX_qgoUafG1blxFRtX340rEkPsHAoRtm_g_9T_pL4Aj3eEHg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2919361658</pqid></control><display><type>article</type><title>A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps</title><source>ProQuest Central UK/Ireland</source><source>SpringerLink Journals - AutoHoldings</source><source>ProQuest Central</source><creator>Das, Debika ; Chakraborty, Ujjal</creator><creatorcontrib>Das, Debika ; Chakraborty, Ujjal</creatorcontrib><description>This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp
+
Si
1-x
Ge
x
layer. It offers an ON current of 1.16 × 10
−4
A/μm providing a high ON/OFF ratio of 3.49 × 10
12
and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp
+
Si
1-x
Ge
x
layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (g
m
/I
D
) behaviour. The high ratio of obtained g
m
/I
D
makes it compatible for future low power applications.</description><identifier>ISSN: 1876-990X</identifier><identifier>EISSN: 1876-9918</identifier><identifier>DOI: 10.1007/s12633-020-00488-0</identifier><language>eng</language><publisher>Dordrecht: Springer Netherlands</publisher><subject>Chemistry ; Chemistry and Materials Science ; Electric fields ; Electrical noise ; Environmental Chemistry ; Flicker ; Germanium ; Heterojunctions ; Impact analysis ; Inorganic Chemistry ; Lasers ; Materials Science ; Optical Devices ; Optics ; Original Paper ; Photonics ; Polymer Sciences ; Silicon ; Silicon germanides ; SOI (semiconductors) ; Thickness ; Transconductance ; Tunnels</subject><ispartof>SILICON, 2021-03, Vol.13 (3), p.787-798</ispartof><rights>Springer Nature B.V. 2020</rights><rights>Springer Nature B.V. 2020.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c319t-a4be13654d9887363ecd1bd669ee8ecc9f8c5eef437abe6201546b91f9632c0a3</citedby><cites>FETCH-LOGICAL-c319t-a4be13654d9887363ecd1bd669ee8ecc9f8c5eef437abe6201546b91f9632c0a3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s12633-020-00488-0$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://www.proquest.com/docview/2919361658?pq-origsite=primo$$EHTML$$P50$$Gproquest$$H</linktohtml><link.rule.ids>314,780,784,21387,27923,27924,33743,41487,42556,43804,51318,64384,64388,72340</link.rule.ids></links><search><creatorcontrib>Das, Debika</creatorcontrib><creatorcontrib>Chakraborty, Ujjal</creatorcontrib><title>A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps</title><title>SILICON</title><addtitle>Silicon</addtitle><description>This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp
+
Si
1-x
Ge
x
layer. It offers an ON current of 1.16 × 10
−4
A/μm providing a high ON/OFF ratio of 3.49 × 10
12
and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp
+
Si
1-x
Ge
x
layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (g
m
/I
D
) behaviour. The high ratio of obtained g
m
/I
D
makes it compatible for future low power applications.</description><subject>Chemistry</subject><subject>Chemistry and Materials Science</subject><subject>Electric fields</subject><subject>Electrical noise</subject><subject>Environmental Chemistry</subject><subject>Flicker</subject><subject>Germanium</subject><subject>Heterojunctions</subject><subject>Impact analysis</subject><subject>Inorganic Chemistry</subject><subject>Lasers</subject><subject>Materials Science</subject><subject>Optical Devices</subject><subject>Optics</subject><subject>Original Paper</subject><subject>Photonics</subject><subject>Polymer Sciences</subject><subject>Silicon</subject><subject>Silicon germanides</subject><subject>SOI (semiconductors)</subject><subject>Thickness</subject><subject>Transconductance</subject><subject>Tunnels</subject><issn>1876-990X</issn><issn>1876-9918</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>AFKRA</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><recordid>eNp9kNFKwzAUhoMoOOZewKuA19WkadPkcmzODYYbbIJ3IU1PpbNLZtJe7AF8bzMneue5yQl8_8fhR-iWkntKSPEQaMoZS0hKEkIyIRJygQZUFDyRkorL3528XqNRCDsSh6WF4HKAPsd40_XVETuLp71u8bSBFkznG4PXzrxDh-fQgXe73pquidRmtcDb3lpo8exxi9fga-f32hrA2lZ41jYx5fGzawLgsdXtMTQBNxavPQQ4Ya7GCxudtY6frdeHcIOuat0GGP28Q_QS3ZN5slw9LSbjZWIYlV2isxIo43lWSSEKxhmYipYV5xJAgDGyFiYHqDNW6BJ4Smie8VLSWnKWGqLZEN2dvQfvPnoIndq53scbg0ollYxTnotIpWfKeBeCh1odfLPX_qgoUafG1blxFRtX340rEkPsHAoRtm_g_9T_pL4Aj3eEHg</recordid><startdate>20210301</startdate><enddate>20210301</enddate><creator>Das, Debika</creator><creator>Chakraborty, Ujjal</creator><general>Springer Netherlands</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>AFKRA</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>D1I</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>KB.</scope><scope>PDBOC</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope></search><sort><creationdate>20210301</creationdate><title>A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps</title><author>Das, Debika ; Chakraborty, Ujjal</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c319t-a4be13654d9887363ecd1bd669ee8ecc9f8c5eef437abe6201546b91f9632c0a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Chemistry</topic><topic>Chemistry and Materials Science</topic><topic>Electric fields</topic><topic>Electrical noise</topic><topic>Environmental Chemistry</topic><topic>Flicker</topic><topic>Germanium</topic><topic>Heterojunctions</topic><topic>Impact analysis</topic><topic>Inorganic Chemistry</topic><topic>Lasers</topic><topic>Materials Science</topic><topic>Optical Devices</topic><topic>Optics</topic><topic>Original Paper</topic><topic>Photonics</topic><topic>Polymer Sciences</topic><topic>Silicon</topic><topic>Silicon germanides</topic><topic>SOI (semiconductors)</topic><topic>Thickness</topic><topic>Transconductance</topic><topic>Tunnels</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Das, Debika</creatorcontrib><creatorcontrib>Chakraborty, Ujjal</creatorcontrib><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Materials Science Collection</collection><collection>ProQuest Central Korea</collection><collection>SciTech Premium Collection</collection><collection>Materials Science Database</collection><collection>Materials Science Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><jtitle>SILICON</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Das, Debika</au><au>Chakraborty, Ujjal</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps</atitle><jtitle>SILICON</jtitle><stitle>Silicon</stitle><date>2021-03-01</date><risdate>2021</risdate><volume>13</volume><issue>3</issue><spage>787</spage><epage>798</epage><pages>787-798</pages><issn>1876-990X</issn><eissn>1876-9918</eissn><abstract>This communication presents the performance analysis and impact of low frequency flicker noise on a dual dielectric pocket heterojunction silicon on insulator (SOI) tunnel FET (TFET). The proposed TFET structure is well optimized for different gate-source underlap length and various thickness of δp
+
Si
1-x
Ge
x
layer. It offers an ON current of 1.16 × 10
−4
A/μm providing a high ON/OFF ratio of 3.49 × 10
12
and a super steeper sub-threshold swing of 2 mV/dec. The device performance is investigated with concern to interface traps while both Uniform and Gaussian trap distributions are considered. The analyses specify that the proposed device is insusceptible to ON current degradation in presence of interface traps in comparison to OFF current behaviour. Electrical noise performance is examined in presence of interface traps and different mole fraction of germanium (Ge) in δp
+
Si
1-x
Ge
x
layer. The device is further tested for its parasitic capacitances and transconductance to drain current ratio (g
m
/I
D
) behaviour. The high ratio of obtained g
m
/I
D
makes it compatible for future low power applications.</abstract><cop>Dordrecht</cop><pub>Springer Netherlands</pub><doi>10.1007/s12633-020-00488-0</doi><tpages>12</tpages></addata></record> |
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| language | eng |
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| source | ProQuest Central UK/Ireland; SpringerLink Journals - AutoHoldings; ProQuest Central |
| subjects | Chemistry Chemistry and Materials Science Electric fields Electrical noise Environmental Chemistry Flicker Germanium Heterojunctions Impact analysis Inorganic Chemistry Lasers Materials Science Optical Devices Optics Original Paper Photonics Polymer Sciences Silicon Silicon germanides SOI (semiconductors) Thickness Transconductance Tunnels |
| title | A Study on Dual Dielectric Pocket Heterojunction SOI Tunnel FET Performance and Flicker Noise Analysis in Presence of Interface Traps |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T02%3A45%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Study%20on%20Dual%20Dielectric%20Pocket%20Heterojunction%20SOI%20Tunnel%20FET%20Performance%20and%20Flicker%20Noise%20Analysis%20in%20Presence%20of%20Interface%20Traps&rft.jtitle=SILICON&rft.au=Das,%20Debika&rft.date=2021-03-01&rft.volume=13&rft.issue=3&rft.spage=787&rft.epage=798&rft.pages=787-798&rft.issn=1876-990X&rft.eissn=1876-9918&rft_id=info:doi/10.1007/s12633-020-00488-0&rft_dat=%3Cproquest_cross%3E2919361658%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2919361658&rft_id=info:pmid/&rfr_iscdi=true |