SVM based layout retargeting for fast and regularized inverse lithography
Inverse lithography technology (ILT), also known as pixel-based optical proximity correction (PB-OPC), has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete e...
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description | Inverse lithography technology (ILT), also known as pixel-based optical proximity correction (PB-OPC), has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the tradi-tional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine (SVM) based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manu-facturability is another critical issue in ILT;however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT (LSB-ILT) algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%, respectively. |
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By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the tradi-tional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine (SVM) based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manu-facturability is another critical issue in ILT;however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT (LSB-ILT) algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%, respectively.</description><identifier>ISSN: 1869-1951</identifier><identifier>ISSN: 2095-9184</identifier><identifier>EISSN: 1869-196X</identifier><identifier>EISSN: 2095-9230</identifier><identifier>DOI: 10.1631/jzus.C1300357</identifier><language>eng</language><publisher>Heidelberg: Zhejiang University Press</publisher><subject>Algorithms ; Communications Engineering ; Computer Hardware ; Computer Science ; Computer Systems Organization and Communication Networks ; Convergence ; Electrical Engineering ; Electronics and Microelectronics ; Instrumentation ; Inverse problems ; Layouts ; Lithography ; Manufacturability ; Networks ; Optimization ; Pixels ; Solution space ; Spatial filtering ; Support vector machines</subject><ispartof>Frontiers of information technology & electronic engineering, 2014-05, Vol.15 (5), p.390-400</ispartof><rights>Journal of Zhejiang University Science Editorial Office and Springer-Verlag Berlin Heidelberg 2014</rights><rights>Journal of Zhejiang University Science Editorial Office and Springer-Verlag Berlin Heidelberg 2014.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c330t-b5748f1634fe5be15c7e8a3e2f7accb4e62710d09a4476017256b19491cb46993</citedby><cites>FETCH-LOGICAL-c330t-b5748f1634fe5be15c7e8a3e2f7accb4e62710d09a4476017256b19491cb46993</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Uhttp://image.cqvip.com/vip1000/qk/89589X/89589X.jpg</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1631/jzus.C1300357$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://www.proquest.com/docview/2918723645?pq-origsite=primo$$EHTML$$P50$$Gproquest$$H</linktohtml><link.rule.ids>314,780,784,21388,27924,27925,33744,41488,42557,43805,51319,64385,64389,72469</link.rule.ids></links><search><creatorcontrib>Luo, Kai-sheng</creatorcontrib><creatorcontrib>Shi, Zheng</creatorcontrib><creatorcontrib>Yan, Xiao-lang</creatorcontrib><creatorcontrib>Geng, Zhen</creatorcontrib><title>SVM based layout retargeting for fast and regularized inverse lithography</title><title>Frontiers of information technology & electronic engineering</title><addtitle>J. Zhejiang Univ. - Sci. C</addtitle><addtitle>Journal of zhejiang university science</addtitle><description>Inverse lithography technology (ILT), also known as pixel-based optical proximity correction (PB-OPC), has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the tradi-tional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine (SVM) based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manu-facturability is another critical issue in ILT;however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT (LSB-ILT) algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%, respectively.</description><subject>Algorithms</subject><subject>Communications Engineering</subject><subject>Computer Hardware</subject><subject>Computer Science</subject><subject>Computer Systems Organization and Communication Networks</subject><subject>Convergence</subject><subject>Electrical Engineering</subject><subject>Electronics and Microelectronics</subject><subject>Instrumentation</subject><subject>Inverse problems</subject><subject>Layouts</subject><subject>Lithography</subject><subject>Manufacturability</subject><subject>Networks</subject><subject>Optimization</subject><subject>Pixels</subject><subject>Solution space</subject><subject>Spatial filtering</subject><subject>Support vector machines</subject><issn>1869-1951</issn><issn>2095-9184</issn><issn>1869-196X</issn><issn>2095-9230</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp1kEtLAzEUhYMoWGqX7iOupyaT12QpRW2h4sIH7kJmmkynjJM2yQjtrzelta5c3Qv3O-dcDgDXGI0xJ_hutevDeIIJQoSJMzDABZcZlvzz_LQzfAlGIawQ2kNMcjIAs9ePZ1jqYBaw1VvXR-hN1L42selqaJ2HVocIdbdIh7pvtW92iW26b-ODgW0Tl672er3cXoELq9tgRsc5BO-PD2-TaTZ_eZpN7udZRQiKWckELWx6mVrDSoNZJUyhicmt0FVVUsNzgdECSU2p4AiLnPESSypxOnIpyRDcHnzX3m16E6Jaud53KVLlEhciJ5yyRGUHqvIuBG-sWvvmS_utwkjtC1P7wtRvYYkfH_iQuK42_s_1P8HNMWDpunqTNKcEKrkUjBbkB37FeNk</recordid><startdate>20140501</startdate><enddate>20140501</enddate><creator>Luo, Kai-sheng</creator><creator>Shi, Zheng</creator><creator>Yan, Xiao-lang</creator><creator>Geng, Zhen</creator><general>Zhejiang University Press</general><general>Springer Nature B.V</general><scope>2RA</scope><scope>92L</scope><scope>CQIGP</scope><scope>~WA</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>L6V</scope><scope>M7S</scope><scope>P5Z</scope><scope>P62</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PTHSS</scope></search><sort><creationdate>20140501</creationdate><title>SVM based layout retargeting for fast and regularized inverse lithography</title><author>Luo, Kai-sheng ; Shi, Zheng ; Yan, Xiao-lang ; Geng, Zhen</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c330t-b5748f1634fe5be15c7e8a3e2f7accb4e62710d09a4476017256b19491cb46993</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Algorithms</topic><topic>Communications Engineering</topic><topic>Computer Hardware</topic><topic>Computer Science</topic><topic>Computer Systems Organization and Communication Networks</topic><topic>Convergence</topic><topic>Electrical Engineering</topic><topic>Electronics and Microelectronics</topic><topic>Instrumentation</topic><topic>Inverse problems</topic><topic>Layouts</topic><topic>Lithography</topic><topic>Manufacturability</topic><topic>Networks</topic><topic>Optimization</topic><topic>Pixels</topic><topic>Solution space</topic><topic>Spatial filtering</topic><topic>Support vector machines</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Luo, Kai-sheng</creatorcontrib><creatorcontrib>Shi, Zheng</creatorcontrib><creatorcontrib>Yan, Xiao-lang</creatorcontrib><creatorcontrib>Geng, Zhen</creatorcontrib><collection>中文科技期刊数据库</collection><collection>中文科技期刊数据库-CALIS站点</collection><collection>中文科技期刊数据库-7.0平台</collection><collection>中文科技期刊数据库- 镜像站点</collection><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>ProQuest Engineering Collection</collection><collection>Engineering Database</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>Engineering Collection</collection><jtitle>Frontiers of information technology & electronic engineering</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Luo, Kai-sheng</au><au>Shi, Zheng</au><au>Yan, Xiao-lang</au><au>Geng, Zhen</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>SVM based layout retargeting for fast and regularized inverse lithography</atitle><jtitle>Frontiers of information technology & electronic engineering</jtitle><stitle>J. Zhejiang Univ. - Sci. C</stitle><addtitle>Journal of zhejiang university science</addtitle><date>2014-05-01</date><risdate>2014</risdate><volume>15</volume><issue>5</issue><spage>390</spage><epage>400</epage><pages>390-400</pages><issn>1869-1951</issn><issn>2095-9184</issn><eissn>1869-196X</eissn><eissn>2095-9230</eissn><abstract>Inverse lithography technology (ILT), also known as pixel-based optical proximity correction (PB-OPC), has shown promising capability in pushing the current 193 nm lithography to its limit. By treating the mask optimization process as an inverse problem in lithography, ILT provides a more complete exploration of the solution space and better pattern fidelity than the tradi-tional edge-based OPC. However, the existing methods of ILT are extremely time-consuming due to the slow convergence of the optimization process. To address this issue, in this paper we propose a support vector machine (SVM) based layout retargeting method for ILT, which is designed to generate a good initial input mask for the optimization process and promote the convergence speed. Supervised by optimized masks of training layouts generated by conventional ILT, SVM models are learned and used to predict the initial pixel values in the‘undefined areas’ of the new layout. By this process, an initial input mask close to the final optimized mask of the new layout is generated, which reduces iterations needed in the following optimization process. Manu-facturability is another critical issue in ILT;however, the mask generated by our layout retargeting method is quite irregular due to the prediction inaccuracy of the SVM models. To compensate for this drawback, a spatial filter is employed to regularize the retargeted mask for complexity reduction. We implemented our layout retargeting method with a regularized level-set based ILT (LSB-ILT) algorithm under partially coherent illumination conditions. Experimental results show that with an initial input mask generated by our layout retargeting method, the number of iterations needed in the optimization process and runtime of the whole process in ILT are reduced by 70.8%and 69.0%, respectively.</abstract><cop>Heidelberg</cop><pub>Zhejiang University Press</pub><doi>10.1631/jzus.C1300357</doi><tpages>11</tpages></addata></record> |
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subjects | Algorithms Communications Engineering Computer Hardware Computer Science Computer Systems Organization and Communication Networks Convergence Electrical Engineering Electronics and Microelectronics Instrumentation Inverse problems Layouts Lithography Manufacturability Networks Optimization Pixels Solution space Spatial filtering Support vector machines |
title | SVM based layout retargeting for fast and regularized inverse lithography |
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