Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders

This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of in...

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Veröffentlicht in:	Journal of real-time image processing 2019-12, Vol.16 (6), p.2173-2187
Hauptverfasser:	Ahn, Yong-Jo, Yoo, Jonghun, Jo, Hyun-Ho, Sim, Donggyu
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive sampling Algorithms Coding standards Computer Graphics Computer Science Decoders Decoding Digital signal processors Efficiency Image Processing and Computer Vision Microprocessors Multimedia Information Systems Original Research Paper Pattern Recognition Reconfiguration Signal,Image and Speech Processing Software Video compression
Online-Zugang:	Volltext
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