Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders
This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of in...
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| Veröffentlicht in: | Journal of real-time image processing 2019-12, Vol.16 (6), p.2173-2187 |
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| container_title | Journal of real-time image processing |
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| creator | Ahn, Yong-Jo Yoo, Jonghun Jo, Hyun-Ho Sim, Donggyu |
| description | This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of inverse transform, pixel reconstruction, de-blocking filter and sample adaptive offset modules. To enable efficient software pipelining, several very-long instruction-word-based intrinsics are designed in order to maximize the parallelization rather than the computational acceleration. We found that the HEVC decoder with the proposed intrinsics yields 2.3 times faster in running clock cycle than a decoder that does not use the intrinsics. In addition, the HEVC decoder with CGA pipelining algorithms executes 10.9 times faster than that without the CGA mode. |
| doi_str_mv | 10.1007/s11554-017-0729-9 |
| format | Article |
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In addition, the HEVC decoder with CGA pipelining algorithms executes 10.9 times faster than that without the CGA mode.</description><identifier>ISSN: 1861-8200</identifier><identifier>EISSN: 1861-8219</identifier><identifier>DOI: 10.1007/s11554-017-0729-9</identifier><language>eng</language><publisher>Berlin/Heidelberg: Springer Berlin Heidelberg</publisher><subject>Adaptive sampling ; Algorithms ; Coding standards ; Computer Graphics ; Computer Science ; Decoders ; Decoding ; Digital signal processors ; Efficiency ; Image Processing and Computer Vision ; Microprocessors ; Multimedia Information Systems ; Original Research Paper ; Pattern Recognition ; Reconfiguration ; Signal,Image and Speech Processing ; Software ; Video compression</subject><ispartof>Journal of real-time image processing, 2019-12, Vol.16 (6), p.2173-2187</ispartof><rights>Springer-Verlag GmbH Germany 2017</rights><rights>Springer-Verlag GmbH Germany 2017.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c268t-ca28d2d2fab367c29d6c89326dadeed7151f6e074ced81891c049512b3834bb43</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s11554-017-0729-9$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://www.proquest.com/docview/2918674177?pq-origsite=primo$$EHTML$$P50$$Gproquest$$H</linktohtml><link.rule.ids>314,780,784,21388,27924,27925,33744,41488,42557,43805,51319,64385,64389,72469</link.rule.ids></links><search><creatorcontrib>Ahn, Yong-Jo</creatorcontrib><creatorcontrib>Yoo, Jonghun</creatorcontrib><creatorcontrib>Jo, Hyun-Ho</creatorcontrib><creatorcontrib>Sim, Donggyu</creatorcontrib><title>Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders</title><title>Journal of real-time image processing</title><addtitle>J Real-Time Image Proc</addtitle><description>This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of inverse transform, pixel reconstruction, de-blocking filter and sample adaptive offset modules. To enable efficient software pipelining, several very-long instruction-word-based intrinsics are designed in order to maximize the parallelization rather than the computational acceleration. We found that the HEVC decoder with the proposed intrinsics yields 2.3 times faster in running clock cycle than a decoder that does not use the intrinsics. In addition, the HEVC decoder with CGA pipelining algorithms executes 10.9 times faster than that without the CGA mode.</description><subject>Adaptive sampling</subject><subject>Algorithms</subject><subject>Coding standards</subject><subject>Computer Graphics</subject><subject>Computer Science</subject><subject>Decoders</subject><subject>Decoding</subject><subject>Digital signal processors</subject><subject>Efficiency</subject><subject>Image Processing and Computer Vision</subject><subject>Microprocessors</subject><subject>Multimedia Information Systems</subject><subject>Original Research Paper</subject><subject>Pattern Recognition</subject><subject>Reconfiguration</subject><subject>Signal,Image and Speech Processing</subject><subject>Software</subject><subject>Video compression</subject><issn>1861-8200</issn><issn>1861-8219</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp1kE1LAzEQhoMoWKs_wFvA82omu5uPY1lqKwge_LiGbJKtKTW7JluK_96UFT15GGYOzzszPAhdA7kFQvhdAqjrqiDAC8KpLOQJmoFgUAgK8vR3JuQcXaS0JYRxVtYzZJ_7bjzo6PDgB7fzwYcNPvjxHTerBdbB4iH2Q5-cxT6M0YfkTcJ9wBpHZ_rQ-c0-6nbnjpxxKfURd7nWy7cG20xYF9MlOuv0Lrmrnz5Hr_fLl2ZdPD6tHprFY2EoE2NhNBWWWtrptmTcUGmZEbKkzGrrnOVQQ8cc4ZVxVoCQYEgla6BtKcqqbatyjm6mvfmXz71Lo9r2-xjySUVlNsAr4DxTMFEm9ilF16kh-g8dvxQQdZSpJpkqy1RHmUrmDJ0yKbNh4-Lf5v9D38vLd-k</recordid><startdate>20191201</startdate><enddate>20191201</enddate><creator>Ahn, Yong-Jo</creator><creator>Yoo, Jonghun</creator><creator>Jo, Hyun-Ho</creator><creator>Sim, Donggyu</creator><general>Springer Berlin Heidelberg</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>P5Z</scope><scope>P62</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope></search><sort><creationdate>20191201</creationdate><title>Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders</title><author>Ahn, Yong-Jo ; Yoo, Jonghun ; Jo, Hyun-Ho ; Sim, Donggyu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c268t-ca28d2d2fab367c29d6c89326dadeed7151f6e074ced81891c049512b3834bb43</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Adaptive sampling</topic><topic>Algorithms</topic><topic>Coding standards</topic><topic>Computer Graphics</topic><topic>Computer Science</topic><topic>Decoders</topic><topic>Decoding</topic><topic>Digital signal processors</topic><topic>Efficiency</topic><topic>Image Processing and Computer Vision</topic><topic>Microprocessors</topic><topic>Multimedia Information Systems</topic><topic>Original Research Paper</topic><topic>Pattern Recognition</topic><topic>Reconfiguration</topic><topic>Signal,Image and Speech Processing</topic><topic>Software</topic><topic>Video compression</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ahn, Yong-Jo</creatorcontrib><creatorcontrib>Yoo, Jonghun</creatorcontrib><creatorcontrib>Jo, Hyun-Ho</creatorcontrib><creatorcontrib>Sim, Donggyu</creatorcontrib><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><jtitle>Journal of real-time image processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Ahn, Yong-Jo</au><au>Yoo, Jonghun</au><au>Jo, Hyun-Ho</au><au>Sim, Donggyu</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders</atitle><jtitle>Journal of real-time image processing</jtitle><stitle>J Real-Time Image Proc</stitle><date>2019-12-01</date><risdate>2019</risdate><volume>16</volume><issue>6</issue><spage>2173</spage><epage>2187</epage><pages>2173-2187</pages><issn>1861-8200</issn><eissn>1861-8219</eissn><abstract>This work proposes several intrinsics on a reconfigurable processor intended for HEVC decoding and software pipelining algorithms with a coarse-grained array (CGA) architecture as well as the proposed intrinsic instructions. Software pipelining algorithms are developed for the CGA acceleration of inverse transform, pixel reconstruction, de-blocking filter and sample adaptive offset modules. To enable efficient software pipelining, several very-long instruction-word-based intrinsics are designed in order to maximize the parallelization rather than the computational acceleration. We found that the HEVC decoder with the proposed intrinsics yields 2.3 times faster in running clock cycle than a decoder that does not use the intrinsics. In addition, the HEVC decoder with CGA pipelining algorithms executes 10.9 times faster than that without the CGA mode.</abstract><cop>Berlin/Heidelberg</cop><pub>Springer Berlin Heidelberg</pub><doi>10.1007/s11554-017-0729-9</doi><tpages>15</tpages></addata></record> |
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| subjects | Adaptive sampling Algorithms Coding standards Computer Graphics Computer Science Decoders Decoding Digital signal processors Efficiency Image Processing and Computer Vision Microprocessors Multimedia Information Systems Original Research Paper Pattern Recognition Reconfiguration Signal,Image and Speech Processing Software Video compression |
| title | Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders |
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