Junctionless FETs based on a silicon-on-insulator architecture with a buried metal fin for multi-threshold operation
In this paper, an n-channel junctionless FinFET (JL FinFET) based on a silicon-on-insulator (SOI) architecture with a buried metal fin (BMF) is presented. We show that the BMF with a suitable work function of the proposed BMF-SOI-JL FinFET device can control the channel electrostatic field by employ...
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| Veröffentlicht in: | Journal of computational electronics 2022-12, Vol.21 (6), p.1250-1261 |
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| creator | Singh, Dipak Kumar Nagar, Bal Chand Akram, M. W. |
| description | In this paper, an n-channel junctionless FinFET (JL FinFET) based on a silicon-on-insulator (SOI) architecture with a buried metal fin (BMF) is presented. We show that the BMF with a suitable work function of the proposed BMF-SOI-JL FinFET device can control the channel electrostatic field by employing a Schottky junction effectively. The enhanced association of potential between BMF and the channel combined with gate electric field makes it worthy for multi-threshold and dynamic threshold (DT) operation. Additionally, the biasing of the BMF projects the broad range of threshold voltage (
V
TH
) regulation with a high value of body factor (
γ
). The proposed device demonstrates
γ
enhancement compared to a fin body (FB)-JL FET and conventional SOI-JL FinFETs under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to a BMF-SOI-JL FinFET without DT. This paper imparts a viable option for low-power applications with multi-threshold operation and high switching speed applications with DT operation. |
| doi_str_mv | 10.1007/s10825-022-01948-z |
| format | Article |
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V
TH
) regulation with a high value of body factor (
γ
). The proposed device demonstrates
γ
enhancement compared to a fin body (FB)-JL FET and conventional SOI-JL FinFETs under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to a BMF-SOI-JL FinFET without DT. This paper imparts a viable option for low-power applications with multi-threshold operation and high switching speed applications with DT operation.</description><identifier>ISSN: 1569-8025</identifier><identifier>EISSN: 1572-8137</identifier><identifier>DOI: 10.1007/s10825-022-01948-z</identifier><language>eng</language><publisher>New York: Springer US</publisher><subject>Calibration ; Electric fields ; Electrical Engineering ; Engineering ; Mathematical and Computational Engineering ; Mathematical and Computational Physics ; Mechanical Engineering ; Optical and Electronic Materials ; Silicon ; Simulation ; SOI (semiconductors) ; Theoretical ; Threshold voltage ; Work functions</subject><ispartof>Journal of computational electronics, 2022-12, Vol.21 (6), p.1250-1261</ispartof><rights>The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2022. Springer Nature or its licensor holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c200t-9d3e69b9499327ffb3f9febe57db2c87362e00ce833651e3c653f372c92616af3</cites><orcidid>0000-0001-9434-6229</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s10825-022-01948-z$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://www.proquest.com/docview/2918276097?pq-origsite=primo$$EHTML$$P50$$Gproquest$$H</linktohtml><link.rule.ids>314,780,784,21388,27924,27925,33744,41488,42557,43805,51319,64385,64389,72469</link.rule.ids></links><search><creatorcontrib>Singh, Dipak Kumar</creatorcontrib><creatorcontrib>Nagar, Bal Chand</creatorcontrib><creatorcontrib>Akram, M. W.</creatorcontrib><title>Junctionless FETs based on a silicon-on-insulator architecture with a buried metal fin for multi-threshold operation</title><title>Journal of computational electronics</title><addtitle>J Comput Electron</addtitle><description>In this paper, an n-channel junctionless FinFET (JL FinFET) based on a silicon-on-insulator (SOI) architecture with a buried metal fin (BMF) is presented. We show that the BMF with a suitable work function of the proposed BMF-SOI-JL FinFET device can control the channel electrostatic field by employing a Schottky junction effectively. The enhanced association of potential between BMF and the channel combined with gate electric field makes it worthy for multi-threshold and dynamic threshold (DT) operation. Additionally, the biasing of the BMF projects the broad range of threshold voltage (
V
TH
) regulation with a high value of body factor (
γ
). The proposed device demonstrates
γ
enhancement compared to a fin body (FB)-JL FET and conventional SOI-JL FinFETs under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to a BMF-SOI-JL FinFET without DT. This paper imparts a viable option for low-power applications with multi-threshold operation and high switching speed applications with DT operation.</description><subject>Calibration</subject><subject>Electric fields</subject><subject>Electrical Engineering</subject><subject>Engineering</subject><subject>Mathematical and Computational Engineering</subject><subject>Mathematical and Computational Physics</subject><subject>Mechanical Engineering</subject><subject>Optical and Electronic Materials</subject><subject>Silicon</subject><subject>Simulation</subject><subject>SOI (semiconductors)</subject><subject>Theoretical</subject><subject>Threshold voltage</subject><subject>Work functions</subject><issn>1569-8025</issn><issn>1572-8137</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp9kMtKAzEYhQdRsFZfwFXAdTSXzmSylOKVghtdh0z6x0mZZmouiH0an8UnM7WCOyHwZ_Gdc-CrqnNKLikh4ipS0rIaE8YwoXLW4u1BNaG1YLilXBzu_o3ELWH1cXUS44oQRtiMTqr8mL1JbvQDxIhub54j6nSEJRo90l-f0Q3OjB6X53zMg05jQDqY3iUwKQdA7y71SKMuB1dSa0h6QNZ5ZAu4zkNyOPUBYj8OpXMDQe_GTqsjq4cIZ793Wr2U6fk9XjzdPcyvF9gwQhKWSw6N7ORMSs6EtR230kIHtVh2zLSCNwwIMdBy3tQUuGlqbrlgRrKGNtryaXWx792E8S1DTGo15uDLpGKStkw0RIpCsT1lwhhjAKs2wa11-FCUqJ1etderil71o1dtS4jvQ7HA_hXCX_U_qW9zd4Ca</recordid><startdate>20221201</startdate><enddate>20221201</enddate><creator>Singh, Dipak Kumar</creator><creator>Nagar, Bal Chand</creator><creator>Akram, M. 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W.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Junctionless FETs based on a silicon-on-insulator architecture with a buried metal fin for multi-threshold operation</atitle><jtitle>Journal of computational electronics</jtitle><stitle>J Comput Electron</stitle><date>2022-12-01</date><risdate>2022</risdate><volume>21</volume><issue>6</issue><spage>1250</spage><epage>1261</epage><pages>1250-1261</pages><issn>1569-8025</issn><eissn>1572-8137</eissn><abstract>In this paper, an n-channel junctionless FinFET (JL FinFET) based on a silicon-on-insulator (SOI) architecture with a buried metal fin (BMF) is presented. We show that the BMF with a suitable work function of the proposed BMF-SOI-JL FinFET device can control the channel electrostatic field by employing a Schottky junction effectively. The enhanced association of potential between BMF and the channel combined with gate electric field makes it worthy for multi-threshold and dynamic threshold (DT) operation. Additionally, the biasing of the BMF projects the broad range of threshold voltage (
V
TH
) regulation with a high value of body factor (
γ
). The proposed device demonstrates
γ
enhancement compared to a fin body (FB)-JL FET and conventional SOI-JL FinFETs under identical conditions due to constant potential coupling. The DT mode of operation shows a 73% improvement in ON-state current in addition to reduced subthreshold swing contrast to a BMF-SOI-JL FinFET without DT. This paper imparts a viable option for low-power applications with multi-threshold operation and high switching speed applications with DT operation.</abstract><cop>New York</cop><pub>Springer US</pub><doi>10.1007/s10825-022-01948-z</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0001-9434-6229</orcidid></addata></record> |
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| subjects | Calibration Electric fields Electrical Engineering Engineering Mathematical and Computational Engineering Mathematical and Computational Physics Mechanical Engineering Optical and Electronic Materials Silicon Simulation SOI (semiconductors) Theoretical Threshold voltage Work functions |
| title | Junctionless FETs based on a silicon-on-insulator architecture with a buried metal fin for multi-threshold operation |
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