An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems
This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy...
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Veröffentlicht in: | IEEE solid-state circuits letters 2024, Vol.7, p.30-33 |
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creator | Zhang, Qirui An, Hyochan Bejarano-Carbo, Andrea Kim, Hun-Seok Blaauw, David Sylvester, Dennis |
description | This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by [Formula Omitted] at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only [Formula Omitted], with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings [Formula Omitted] reduction to the overall energy for regressing an image of change-detected region of interest. |
doi_str_mv | 10.1109/LSSC.2023.3344699 |
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The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by [Formula Omitted] at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only [Formula Omitted], with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. 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(IEEE) 2024</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c225t-63bb17982347829eed1b03ddb8cb918b36aafe92c3afab1750d7d74df4d7e6aa3</cites><orcidid>0000-0002-6322-025X ; 0000-0002-7269-4545 ; 0000-0003-2598-0458 ; 0000-0002-6658-5502 ; 0000-0001-8113-3558 ; 0000-0001-6744-7075</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,4024,27923,27924,27925</link.rule.ids></links><search><creatorcontrib>Zhang, Qirui</creatorcontrib><creatorcontrib>An, Hyochan</creatorcontrib><creatorcontrib>Bejarano-Carbo, Andrea</creatorcontrib><creatorcontrib>Kim, Hun-Seok</creatorcontrib><creatorcontrib>Blaauw, David</creatorcontrib><creatorcontrib>Sylvester, Dennis</creatorcontrib><title>An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems</title><title>IEEE solid-state circuits letters</title><description>This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by [Formula Omitted] at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only [Formula Omitted], with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings [Formula Omitted] reduction to the overall energy for regressing an image of change-detected region of interest.</description><subject>Algorithms</subject><subject>Change detection</subject><subject>Codec</subject><subject>Image compression</subject><subject>Reconfiguration</subject><issn>2573-9603</issn><issn>2573-9603</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2024</creationdate><recordtype>article</recordtype><recordid>eNpNkE1rwkAQhpfSQsX6A3pb6DlxP_K1x5BqDQgtqL0um2QikSRrd6Piv--meuhh5h1435mBB6FXSnxKiZivN5vMZ4Rxn_MgiIR4QBMWxtwTEeGP_-ZnNLP2QAihgkacJBN0Tnu8awejWn3xvvQFDF75LArm6XeG894Z3tKoDnDeqT3gTHdHA9Y2usdpWUILRg3a4NqVS0PbNnvoB7w4u-69m8YpzvX2b73p93hztQN09gU91aq1MLvrFO2Wi2228tafH3mWrr2SsXDwIl4UNBYJ40GcMAFQ0YLwqiqSshA0KXikVA2ClVzVyiVDUsVVHFR1UMXgPD5Fb7e7R6N_TmAHedAn07uXkgnqsAQiCV2K3lKl0dYaqOXRNJ0yV0mJHAnLkbAcCcs7Yf4LjBBulw</recordid><startdate>2024</startdate><enddate>2024</enddate><creator>Zhang, Qirui</creator><creator>An, Hyochan</creator><creator>Bejarano-Carbo, Andrea</creator><creator>Kim, Hun-Seok</creator><creator>Blaauw, David</creator><creator>Sylvester, Dennis</creator><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-6322-025X</orcidid><orcidid>https://orcid.org/0000-0002-7269-4545</orcidid><orcidid>https://orcid.org/0000-0003-2598-0458</orcidid><orcidid>https://orcid.org/0000-0002-6658-5502</orcidid><orcidid>https://orcid.org/0000-0001-8113-3558</orcidid><orcidid>https://orcid.org/0000-0001-6744-7075</orcidid></search><sort><creationdate>2024</creationdate><title>An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems</title><author>Zhang, Qirui ; An, Hyochan ; Bejarano-Carbo, Andrea ; Kim, Hun-Seok ; Blaauw, David ; Sylvester, Dennis</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c225t-63bb17982347829eed1b03ddb8cb918b36aafe92c3afab1750d7d74df4d7e6aa3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2024</creationdate><topic>Algorithms</topic><topic>Change detection</topic><topic>Codec</topic><topic>Image compression</topic><topic>Reconfiguration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhang, Qirui</creatorcontrib><creatorcontrib>An, Hyochan</creatorcontrib><creatorcontrib>Bejarano-Carbo, Andrea</creatorcontrib><creatorcontrib>Kim, Hun-Seok</creatorcontrib><creatorcontrib>Blaauw, David</creatorcontrib><creatorcontrib>Sylvester, Dennis</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE solid-state circuits letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Zhang, Qirui</au><au>An, Hyochan</au><au>Bejarano-Carbo, Andrea</au><au>Kim, Hun-Seok</au><au>Blaauw, David</au><au>Sylvester, Dennis</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems</atitle><jtitle>IEEE solid-state circuits letters</jtitle><date>2024</date><risdate>2024</risdate><volume>7</volume><spage>30</spage><epage>33</epage><pages>30-33</pages><issn>2573-9603</issn><eissn>2573-9603</eissn><abstract>This letter presents an ultralow-power (ULP) H.264/AVC intra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB) accesses by [Formula Omitted] at a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in 40 nm, it occupies a mere 0.32 mm2 area with 4-kB SRAM. At 0.6 V and 153 kHz, it consumes only [Formula Omitted], with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings [Formula Omitted] reduction to the overall energy for regressing an image of change-detected region of interest.</abstract><cop>Piscataway</cop><pub>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</pub><doi>10.1109/LSSC.2023.3344699</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-6322-025X</orcidid><orcidid>https://orcid.org/0000-0002-7269-4545</orcidid><orcidid>https://orcid.org/0000-0003-2598-0458</orcidid><orcidid>https://orcid.org/0000-0002-6658-5502</orcidid><orcidid>https://orcid.org/0000-0001-8113-3558</orcidid><orcidid>https://orcid.org/0000-0001-6744-7075</orcidid></addata></record> |
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subjects | Algorithms Change detection Codec Image compression Reconfiguration |
title | An Ultralow-Power H.264/AVC Intra-Frame Image Compression Accelerator for Intelligent Event-Driven IoT Imaging Systems |
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