A Principal Factor of Performance in Decoupled Front-End

One of the performance bottlenecks of a processor is the front-end that supplies instructions. Various techniques, such as cache replacement algorithms and hardware prefetching, have been investigated to facilitate smooth instruction supply at the front-end and to improve processor performance. In t...

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Veröffentlicht in:	IEICE Transactions on Information and Systems 2023/12/01, Vol.E106.D(12), pp.1960-1968
Hauptverfasser:	DEGAWA, Yuya, KOIZUMI, Toru, NAKAMURA, Tomoki, SHIOYA, Ryota, KADOMOTO, Junichiro, IRIE, Hidetsugu, SAKAI, Shuichi
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms instruction fetch Mathematical analysis Mathematical models Microprocessors modeling techniques Processors
Online-Zugang:	Volltext
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