Improved Design for Hardware Implementation of Graph-Based Large Margin Classifiers for Embedded Edge Computing

The number of connected embedded edge computing Internet of Things (IoT) devices has been increasing over the years, contributing to the significant growth of available data in different scenarios. Thereby, machine learning algorithms arise to enable task automation and process optimization based on...

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Veröffentlicht in:	IEEE transaction on neural networks and learning systems 2024-01, Vol.35 (1), p.1320-1329
Hauptverfasser:	Arias-Garcia, Janier, de Souza, Alan Candido, Gade, Liliane, Yudi, Jones, Coelho, Frederico, Castro, Cristiano L., Torres, Luiz C. B., Braga, Antonio P.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Automation Classifiers Complexity Computational modeling Edge computing embedded system Embedded systems Equivalence Field programmable gate arrays Floating point arithmetic FPGA Gabriel graph Hardware hardware design of neural networks Internet of Things Internet of Things (IoT) large margin latency-sensitive applications Learning Machine learning Numerical models Optimization Robustness (mathematics) system-on-a-chip
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