A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector
This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With the proposed time-amplifying phase-frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conven...
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| Veröffentlicht in: | IEEE transactions on microwave theory and techniques 2023-11, Vol.71 (11), p.1-13 |
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| container_title | IEEE transactions on microwave theory and techniques |
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| creator | Geng, Xinlin Ye, Zonglin Xiao, Yao Tian, Yibo Xie, Qian Wang, Zheng |
| description | This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With the proposed time-amplifying phase-frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conventional CPPLL. Moreover, a frequency pull-in capability analysis is carried out to prove that the proposed phase-locked loop (PLL) features a robust lock acquisition performance. The proposed PLL is prototyped in a 65-nm CMOS process, achieving 60-fs rms jitter, 14.48-mW power consumption, and - 252.8-dB FoM _{J} with a 0.45-mm ^{2} active area. |
| doi_str_mv | 10.1109/TMTT.2023.3269572 |
| format | Article |
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With the proposed time-amplifying phase-frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conventional CPPLL. Moreover, a frequency pull-in capability analysis is carried out to prove that the proposed phase-locked loop (PLL) features a robust lock acquisition performance. The proposed PLL is prototyped in a 65-nm CMOS process, achieving 60-fs rms jitter, 14.48-mW power consumption, and <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>252.8-dB FoM<inline-formula> <tex-math notation="LaTeX">_{J}</tex-math> </inline-formula> with a 0.45-mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula> active area.]]></description><identifier>ISSN: 0018-9480</identifier><identifier>EISSN: 1557-9670</identifier><identifier>DOI: 10.1109/TMTT.2023.3269572</identifier><identifier>CODEN: IETMAB</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>1/f noise ; 5G communication ; Amplification ; charge pump phase-locked loop (CPPLL) ; Charge pumps ; Detectors ; Frequency analysis ; frequency synthesizer ; Integers ; Jitter ; Phase error ; Phase frequency detectors ; Phase locked loops ; Phase noise ; Power consumption ; Robustness ; time–amplifying phase–frequency detector (TAPFD) ; ultralow jitter ; Vibration ; Voltage-controlled oscillators</subject><ispartof>IEEE transactions on microwave theory and techniques, 2023-11, Vol.71 (11), p.1-13</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c294t-513c831f74022dd7ab40fb15c4ffde8f133354f8892081802b9cd100abca44213</citedby><cites>FETCH-LOGICAL-c294t-513c831f74022dd7ab40fb15c4ffde8f133354f8892081802b9cd100abca44213</cites><orcidid>0000-0002-5232-0298 ; 0000-0002-8538-348X ; 0000-0002-0680-1592 ; 0000-0002-3994-0652</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10122243$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27928,27929,54762</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10122243$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Geng, Xinlin</creatorcontrib><creatorcontrib>Ye, Zonglin</creatorcontrib><creatorcontrib>Xiao, Yao</creatorcontrib><creatorcontrib>Tian, Yibo</creatorcontrib><creatorcontrib>Xie, Qian</creatorcontrib><creatorcontrib>Wang, Zheng</creatorcontrib><title>A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector</title><title>IEEE transactions on microwave theory and techniques</title><addtitle>TMTT</addtitle><description><![CDATA[This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With the proposed time-amplifying phase-frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conventional CPPLL. Moreover, a frequency pull-in capability analysis is carried out to prove that the proposed phase-locked loop (PLL) features a robust lock acquisition performance. The proposed PLL is prototyped in a 65-nm CMOS process, achieving 60-fs rms jitter, 14.48-mW power consumption, and <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>252.8-dB FoM<inline-formula> <tex-math notation="LaTeX">_{J}</tex-math> </inline-formula> with a 0.45-mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula> active area.]]></description><subject>1/f noise</subject><subject>5G communication</subject><subject>Amplification</subject><subject>charge pump phase-locked loop (CPPLL)</subject><subject>Charge pumps</subject><subject>Detectors</subject><subject>Frequency analysis</subject><subject>frequency synthesizer</subject><subject>Integers</subject><subject>Jitter</subject><subject>Phase error</subject><subject>Phase frequency detectors</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>Power consumption</subject><subject>Robustness</subject><subject>time–amplifying phase–frequency detector (TAPFD)</subject><subject>ultralow jitter</subject><subject>Vibration</subject><subject>Voltage-controlled oscillators</subject><issn>0018-9480</issn><issn>1557-9670</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE9PAjEQxRujiYh-ABMPTTwXO22X7R4R5Y9ZlZj1vNnttlCEXWiLCd793i6Bg6eZyfzem8lD6BZoD4AmD9lrlvUYZbzHWT-JYnaGOhBFMUn6MT1HHUpBkkRIeomuvF-2o4io7KDfAWZRT5Lx5AdP66Dn2pE3PJzN0hQP1MLqb1vPcZ8S47Fbe_xiQ9AOF3WFP5py5wNOG_XVotud9TbYpsaPhdcVbpsCZ3atyWC9WVmzP_jMFu2OjJze7nSt9vhJB61C467RhSlWXt-cahd9jp6z4YSk7-PpcJASxRIRSARcSQ4mFpSxqoqLUlBTQqSEMZWWBjjnkTBSJoxKkJSViaqA0qJUhRAMeBfdH303rmlf8CFfNjtXtydzJmUMAJLFLQVHSrnGe6dNvnF2Xbh9DjQ_pJ0f0s4PaeentFvN3VFjtdb_eGCMCc7_AMA6eUQ</recordid><startdate>20231101</startdate><enddate>20231101</enddate><creator>Geng, Xinlin</creator><creator>Ye, Zonglin</creator><creator>Xiao, Yao</creator><creator>Tian, Yibo</creator><creator>Xie, Qian</creator><creator>Wang, Zheng</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-5232-0298</orcidid><orcidid>https://orcid.org/0000-0002-8538-348X</orcidid><orcidid>https://orcid.org/0000-0002-0680-1592</orcidid><orcidid>https://orcid.org/0000-0002-3994-0652</orcidid></search><sort><creationdate>20231101</creationdate><title>A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector</title><author>Geng, Xinlin ; Ye, Zonglin ; Xiao, Yao ; Tian, Yibo ; Xie, Qian ; Wang, Zheng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c294t-513c831f74022dd7ab40fb15c4ffde8f133354f8892081802b9cd100abca44213</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>1/f noise</topic><topic>5G communication</topic><topic>Amplification</topic><topic>charge pump phase-locked loop (CPPLL)</topic><topic>Charge pumps</topic><topic>Detectors</topic><topic>Frequency analysis</topic><topic>frequency synthesizer</topic><topic>Integers</topic><topic>Jitter</topic><topic>Phase error</topic><topic>Phase frequency detectors</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><topic>Power consumption</topic><topic>Robustness</topic><topic>time–amplifying phase–frequency detector (TAPFD)</topic><topic>ultralow jitter</topic><topic>Vibration</topic><topic>Voltage-controlled oscillators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Geng, Xinlin</creatorcontrib><creatorcontrib>Ye, Zonglin</creatorcontrib><creatorcontrib>Xiao, Yao</creatorcontrib><creatorcontrib>Tian, Yibo</creatorcontrib><creatorcontrib>Xie, Qian</creatorcontrib><creatorcontrib>Wang, Zheng</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on microwave theory and techniques</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Geng, Xinlin</au><au>Ye, Zonglin</au><au>Xiao, Yao</au><au>Tian, Yibo</au><au>Xie, Qian</au><au>Wang, Zheng</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector</atitle><jtitle>IEEE transactions on microwave theory and techniques</jtitle><stitle>TMTT</stitle><date>2023-11-01</date><risdate>2023</risdate><volume>71</volume><issue>11</issue><spage>1</spage><epage>13</epage><pages>1-13</pages><issn>0018-9480</issn><eissn>1557-9670</eissn><coden>IETMAB</coden><abstract><![CDATA[This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With the proposed time-amplifying phase-frequency detector (TAPFD), the in-band noise is greatly suppressed by the phase error amplification gain of TAPFD so as to break the stringent power-noise tradeoff in the conventional CPPLL. Moreover, a frequency pull-in capability analysis is carried out to prove that the proposed phase-locked loop (PLL) features a robust lock acquisition performance. The proposed PLL is prototyped in a 65-nm CMOS process, achieving 60-fs rms jitter, 14.48-mW power consumption, and <inline-formula> <tex-math notation="LaTeX">-</tex-math> </inline-formula>252.8-dB FoM<inline-formula> <tex-math notation="LaTeX">_{J}</tex-math> </inline-formula> with a 0.45-mm<inline-formula> <tex-math notation="LaTeX">^{2}</tex-math> </inline-formula> active area.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TMTT.2023.3269572</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-5232-0298</orcidid><orcidid>https://orcid.org/0000-0002-8538-348X</orcidid><orcidid>https://orcid.org/0000-0002-0680-1592</orcidid><orcidid>https://orcid.org/0000-0002-3994-0652</orcidid></addata></record> |
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| subjects | 1/f noise 5G communication Amplification charge pump phase-locked loop (CPPLL) Charge pumps Detectors Frequency analysis frequency synthesizer Integers Jitter Phase error Phase frequency detectors Phase locked loops Phase noise Power consumption Robustness time–amplifying phase–frequency detector (TAPFD) ultralow jitter Vibration Voltage-controlled oscillators |
| title | A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time-Amplifying Phase-Frequency Detector |
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