An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications
The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2023-09, Vol.70 (9), p.1-8 |
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| container_title | IEEE transactions on circuits and systems. I, Regular papers |
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| creator | Tripathi, Sandeep Choudhary, Sudhanshu Misra, Prasanna Kumar |
| description | The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is 1000 \times less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes 2 \times more energy efficient and 3 \times faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell. |
| doi_str_mv | 10.1109/TCSI.2023.3280193 |
| format | Article |
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Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is 1000<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes 2<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> more energy efficient and 3<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell.]]></description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2023.3280193</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Computation ; Correlation ; Delays ; in-memory-computing (IMC) ; Magnetic tunneling ; Non-volatile SRAM (NVSRAM) ; power analysis (PA) attack ; Power consumption ; Resilience ; side channel attacks ; Static random access memory ; Torque ; Transistors ; Tunnel junctions ; Writing</subject><ispartof>IEEE transactions on circuits and systems. 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(IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c294t-59a18df7d626d13ad110a2b007552559603aec3434585689825bca290ec468413</citedby><cites>FETCH-LOGICAL-c294t-59a18df7d626d13ad110a2b007552559603aec3434585689825bca290ec468413</cites><orcidid>0000-0003-4463-4171 ; 0000-0003-4942-1335 ; 0000-0002-6560-3000</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10144801$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10144801$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tripathi, Sandeep</creatorcontrib><creatorcontrib>Choudhary, Sudhanshu</creatorcontrib><creatorcontrib>Misra, Prasanna Kumar</creatorcontrib><title>An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description><![CDATA[The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is 1000<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes 2<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> more energy efficient and 3<inline-formula> <tex-math notation="LaTeX">\times</tex-math> </inline-formula> faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell.]]></description><subject>Computation</subject><subject>Correlation</subject><subject>Delays</subject><subject>in-memory-computing (IMC)</subject><subject>Magnetic tunneling</subject><subject>Non-volatile SRAM (NVSRAM)</subject><subject>power analysis (PA) attack</subject><subject>Power consumption</subject><subject>Resilience</subject><subject>side channel attacks</subject><subject>Static random access memory</subject><subject>Torque</subject><subject>Transistors</subject><subject>Tunnel junctions</subject><subject>Writing</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkE1LAzEQhoMoWKs_QPAQ8Lw1n9vkuCxVF1qVtnoNaTYrqe3umqSH_nuztAdPMzDPzLw8ANxjNMEYyad1uaomBBE6oUQgLOkFGGHORYYEyi-HnslMpNk1uAlhixCRiOIRmBUtFGv4UcAiRm1-4NIGt3O2jfDta7UsFrDpPKzabGH3nT9mZbfvD9G137Do-50zOrquDbfgqtG7YO_OdQw-n2fr8jWbv79UZTHPDJEsZlxqLOpmWuckrzHVdYquyQahKeeEc5kjqq2hjDIueC6kIHxjdEpqDcsFw3QMHk93e9_9HmyIatsdfJteKiK4mHJMaZ4ofKKM70LwtlG9d3vtjwojNdhSgy012FJnW2nn4bTjrLX_eMxYAugfhrBicA</recordid><startdate>20230901</startdate><enddate>20230901</enddate><creator>Tripathi, Sandeep</creator><creator>Choudhary, Sudhanshu</creator><creator>Misra, Prasanna Kumar</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tripathi, Sandeep</au><au>Choudhary, Sudhanshu</au><au>Misra, Prasanna Kumar</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2023-09-01</date><risdate>2023</risdate><volume>70</volume><issue>9</issue><spage>1</spage><epage>8</epage><pages>1-8</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract><![CDATA[The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. 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| subjects | Computation Correlation Delays in-memory-computing (IMC) Magnetic tunneling Non-volatile SRAM (NVSRAM) power analysis (PA) attack Power consumption Resilience side channel attacks Static random access memory Torque Transistors Tunnel junctions Writing |
| title | An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications |
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