The Microarchitecture of DOJO, Tesla's Exa-Scale Computer

The Tesla-built DOJO system is a scalable solution targeted towards machine learning training applications. It is based on the D1 custom compute chip which packs together 354 independent processors, resulting in 362 TFLOPS of compute and 440 MB of internal static random-access memory storage. While...

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Veröffentlicht in:	IEEE MICRO 2023-05, Vol.43 (3), p.31-39
Hauptverfasser:	Talpes, Emil, Sarma, Debjit Das, Williams, Doug, Arora, Sahil, Kunjan, Thomas, Floering, Benjamin, Jalote, Ankit, Hsiong, Christopher, Poorna, Chandrasekhar, Samant, Vaidehi, Sicilia, John, Nivarti, Anantha Kumar, Ramachandran, Raghuvir, Fischer, Tim, Herzberg, Ben, McGee, Bill, Venkataramanan, Ganesh, Banon, Pete
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Computational modeling Computer architecture Instruction sets Machine learning Microarchitecture Static random access memory Training
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