An In-Memory-Computing Charge-Domain Ternary CNN Classifier

The article presents a charge-domain computing ternary neural network (TNN) classifier with a complete four-layer neural network (NN) on a chip. The proposed ternary network provides 1.5-b resolution (0/ + 1/ - 1) for weights and activations, leading to 3.9 \times fewer operations (OPs) per inference than binary neural network (BNN) for the same Modified National Institute of Standards and Technology (MNIST) accuracy. The 1.5-b multiply-and-accumulate (MAC) is implemented by V_{\text{CM}} -based capacitor switching scheme, which inherently benefits from the reduced signal swing on the capacitive digital-to-analog converter (CDAC). Also, the V_{\text{CM}} -based MAC introduces sparsity during training, resulting in a lower switching rate. The prototype is fabricated in a 40-nm LP CMOS process with an active area of 0.98 mm ^2 , operates at 549 frames/s (FPS), and consumes 96 \mu W. With all OPs on the chip, it achieves 97.1% MNIST accuracy with 0.18 \mu J per classification, which is the smallest to our knowledge for comparable MNIST classification accuracy.