Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node
Single-port (SP) and two-port (TP) static random access memory (SRAM) designs in a 5-nm bulk FinFET node were tested for multicell upset (MCU) vulnerability against alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions with nominal and reduced supply voltages. MCU contributions to singl...
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Veröffentlicht in: | IEEE transactions on nuclear science 2023-04, Vol.70 (4), p.401-409 |
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creator | Pieper, Nicholas J. Xiong, Yoni Feeley, Alexandra Pasternak, John Dodds, Nathaniel Ball, D. R. Bhuva, Bharat L. |
description | Single-port (SP) and two-port (TP) static random access memory (SRAM) designs in a 5-nm bulk FinFET node were tested for multicell upset (MCU) vulnerability against alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions with nominal and reduced supply voltages. MCU contributions to single-event upset (SEU) rates and observed bitline (BL) upset ranges are presented for each particle as a function of supply voltage. Results show that MCUs account for a majority of events from high linear energy transfer (LET) particles and neutrons at lower supply voltages. MCU shapes are shown for various sizes of upset clusters. |
doi_str_mv | 10.1109/TNS.2023.3240318 |
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MCU shapes are shown for various sizes of upset clusters.</description><identifier>ISSN: 0018-9499</identifier><identifier>EISSN: 1558-1578</identifier><identifier>DOI: 10.1109/TNS.2023.3240318</identifier><language>eng</language><publisher>New York: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</publisher><subject>Alpha particles ; Alpha rays ; Energy transfer ; Heavy ions ; Linear energy transfer (LET) ; Neutrons ; Single event upsets ; Static random access memory ; Thermal neutrons</subject><ispartof>IEEE transactions on nuclear science, 2023-04, Vol.70 (4), p.401-409</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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R.</creatorcontrib><creatorcontrib>Bhuva, Bharat L.</creatorcontrib><title>Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node</title><title>IEEE transactions on nuclear science</title><description>Single-port (SP) and two-port (TP) static random access memory (SRAM) designs in a 5-nm bulk FinFET node were tested for multicell upset (MCU) vulnerability against alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions with nominal and reduced supply voltages. MCU contributions to single-event upset (SEU) rates and observed bitline (BL) upset ranges are presented for each particle as a function of supply voltage. Results show that MCUs account for a majority of events from high linear energy transfer (LET) particles and neutrons at lower supply voltages. MCU shapes are shown for various sizes of upset clusters.</description><subject>Alpha particles</subject><subject>Alpha rays</subject><subject>Energy transfer</subject><subject>Heavy ions</subject><subject>Linear energy transfer (LET)</subject><subject>Neutrons</subject><subject>Single event upsets</subject><subject>Static random access memory</subject><subject>Thermal neutrons</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><recordid>eNotkM9LwzAcxYMoWKd3jwHPnd_8bAJe5nAqbBPsdg5pk0Bn186mPey_X8d2ejze4z34IPRMYEoI6NfNOp9SoGzKKAdG1A1KiBAqJSJTtygBICrVXOt79BDjbrRcgEjQW94P7ojbgFdD3Velr2u8PUTfR1w1OP-drbDtscUibfb4faj_8KJqFh8bvG6df0R3wdbRP111grZjNP9Klz-f3_PZMi1pRvqUOp0FR7RSElQWuNSUEldQVgjrLbBSCU4YDYGLIgiZCWWFK5h0VCrPM80m6OWye-ja_8HH3uzaoWvGS0MVMGBSUjW24NIquzbGzgdz6Kq97Y6GgDkzMiMjc2ZkrozYCZ6LVZ8</recordid><startdate>20230401</startdate><enddate>20230401</enddate><creator>Pieper, Nicholas J.</creator><creator>Xiong, Yoni</creator><creator>Feeley, Alexandra</creator><creator>Pasternak, John</creator><creator>Dodds, Nathaniel</creator><creator>Ball, D. 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subjects | Alpha particles Alpha rays Energy transfer Heavy ions Linear energy transfer (LET) Neutrons Single event upsets Static random access memory Thermal neutrons |
title | Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node |
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