Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node

Single-port (SP) and two-port (TP) static random access memory (SRAM) designs in a 5-nm bulk FinFET node were tested for multicell upset (MCU) vulnerability against alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions with nominal and reduced supply voltages. MCU contributions to single-event upset (SEU) rates and observed bitline (BL) upset ranges are presented for each particle as a function of supply voltage. Results show that MCUs account for a majority of events from high linear energy transfer (LET) particles and neutrons at lower supply voltages. MCU shapes are shown for various sizes of upset clusters.