Stress Effects of Interconnecting Metals on Back-End-of-Line Compatible Hf0.5Zr0.5O2 Ferroelectric Capacitors
The back-end-of-line (BEOL) process compatibility is one of the advantages of Hf0.5Zr0.5O2 (HZO)-based ferroelectric (FE) among other kinds of HfO2-doped FEs. However, the impact of stress effect induced by the interconnects during device stacking cannot be ignored. Previous studies about the stress...
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| Veröffentlicht in: | IEEE electron device letters 2023-04, Vol.44 (4), p.602-605 |
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| creator | Jiang, Pengfei Yang, Yang Wei, Wei Gong, Tiancheng Wang, Yuan Chen, Yuting Ding, Yaxin Lv, Shuxian Wang, Boping Chen, Meiwen Wang, Yan Luo, Qing |
| description | The back-end-of-line (BEOL) process compatibility is one of the advantages of Hf0.5Zr0.5O2 (HZO)-based ferroelectric (FE) among other kinds of HfO2-doped FEs. However, the impact of stress effect induced by the interconnects during device stacking cannot be ignored. Previous studies about the stress effect have mainly focused on the metal in direct contact with the FE layer, but have neglected the potential effects of other layers covering the electrodes. In this work, the stress effects of interconnecting metals including Cu and W, which are the most mainstream interconnects in modern integrated circuit (IC) technology, are systematically demonstrated. The capping layers can exert stress on the top electrode (TE), and this stress transfers to the HZO layer during annealing, which affects the crystalline state of HZO films and enhances or suppresses the ferroelectricity. This is verified by the devices' electrical performance, the residual stresses measurements and grazing-angle incidence X-ray diffraction results. The results can guide the selection of the proper annealing timing for large-scale FE memory integration when utilizing the BEOL process with different interconnects. |
| doi_str_mv | 10.1109/LED.2023.3248103 |
| format | Article |
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However, the impact of stress effect induced by the interconnects during device stacking cannot be ignored. Previous studies about the stress effect have mainly focused on the metal in direct contact with the FE layer, but have neglected the potential effects of other layers covering the electrodes. In this work, the stress effects of interconnecting metals including Cu and W, which are the most mainstream interconnects in modern integrated circuit (IC) technology, are systematically demonstrated. The capping layers can exert stress on the top electrode (TE), and this stress transfers to the HZO layer during annealing, which affects the crystalline state of HZO films and enhances or suppresses the ferroelectricity. This is verified by the devices' electrical performance, the residual stresses measurements and grazing-angle incidence X-ray diffraction results. The results can guide the selection of the proper annealing timing for large-scale FE memory integration when utilizing the BEOL process with different interconnects.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2023.3248103</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Annealing ; BEOL ; Capacitors ; Contact stresses ; Copper ; Electric contacts ; Electrodes ; ferroelectric ; Ferroelectric materials ; Ferroelectricity ; HZO ; Integrated circuit interconnections ; Integrated circuits ; interconnecting metal ; Interconnections ; Iron ; Residual stress ; stress effect ; Tin</subject><ispartof>IEEE electron device letters, 2023-04, Vol.44 (4), p.602-605</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><orcidid>0000-0002-2790-7302 ; 0000-0002-7543-8651 ; 0000-0001-7259-3237 ; 0000-0002-1259-6310 ; 0000-0003-1591-6874 ; 0000-0002-3419-4400</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10050514$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10050514$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Jiang, Pengfei</creatorcontrib><creatorcontrib>Yang, Yang</creatorcontrib><creatorcontrib>Wei, Wei</creatorcontrib><creatorcontrib>Gong, Tiancheng</creatorcontrib><creatorcontrib>Wang, Yuan</creatorcontrib><creatorcontrib>Chen, Yuting</creatorcontrib><creatorcontrib>Ding, Yaxin</creatorcontrib><creatorcontrib>Lv, Shuxian</creatorcontrib><creatorcontrib>Wang, Boping</creatorcontrib><creatorcontrib>Chen, Meiwen</creatorcontrib><creatorcontrib>Wang, Yan</creatorcontrib><creatorcontrib>Luo, Qing</creatorcontrib><title>Stress Effects of Interconnecting Metals on Back-End-of-Line Compatible Hf0.5Zr0.5O2 Ferroelectric Capacitors</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>The back-end-of-line (BEOL) process compatibility is one of the advantages of Hf0.5Zr0.5O2 (HZO)-based ferroelectric (FE) among other kinds of HfO2-doped FEs. However, the impact of stress effect induced by the interconnects during device stacking cannot be ignored. Previous studies about the stress effect have mainly focused on the metal in direct contact with the FE layer, but have neglected the potential effects of other layers covering the electrodes. In this work, the stress effects of interconnecting metals including Cu and W, which are the most mainstream interconnects in modern integrated circuit (IC) technology, are systematically demonstrated. The capping layers can exert stress on the top electrode (TE), and this stress transfers to the HZO layer during annealing, which affects the crystalline state of HZO films and enhances or suppresses the ferroelectricity. This is verified by the devices' electrical performance, the residual stresses measurements and grazing-angle incidence X-ray diffraction results. The results can guide the selection of the proper annealing timing for large-scale FE memory integration when utilizing the BEOL process with different interconnects.</description><subject>Annealing</subject><subject>BEOL</subject><subject>Capacitors</subject><subject>Contact stresses</subject><subject>Copper</subject><subject>Electric contacts</subject><subject>Electrodes</subject><subject>ferroelectric</subject><subject>Ferroelectric materials</subject><subject>Ferroelectricity</subject><subject>HZO</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>interconnecting metal</subject><subject>Interconnections</subject><subject>Iron</subject><subject>Residual stress</subject><subject>stress effect</subject><subject>Tin</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNotjTFPwzAUhC0EEqWwMzBYYnZ4L89ukhFKSisFdQAWlsiJn1FKmwQnHfj3RCrLnXR3-k6IW4QIEbKHIn-OYogpolinCHQmZmhMqsAs6FzMINGoCGFxKa6GYQeAWid6Jg5vY-BhkLn3XI-D7LzctCOHumvbKWjaL_nKo91PTSufbP2t8tapzquiaVkuu0Nvx6bas1x7iMxnmGQbyxWH0PF-AoSmlkvb27oZuzBciws_sfjm3-fiY5W_L9eq2L5slo-FapD0qByzxxRtbQxpUzOknFUJmSrTxlIN4Lx2ZDC1MZM3FWNmK5dp5-yCNTmai_sTtw_dz5GHsdx1x9BOl2WcZIBEaUzT6u60api57ENzsOG3RAADBjX9AV2cY60</recordid><startdate>20230401</startdate><enddate>20230401</enddate><creator>Jiang, Pengfei</creator><creator>Yang, Yang</creator><creator>Wei, Wei</creator><creator>Gong, Tiancheng</creator><creator>Wang, Yuan</creator><creator>Chen, Yuting</creator><creator>Ding, Yaxin</creator><creator>Lv, Shuxian</creator><creator>Wang, Boping</creator><creator>Chen, Meiwen</creator><creator>Wang, Yan</creator><creator>Luo, Qing</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| subjects | Annealing BEOL Capacitors Contact stresses Copper Electric contacts Electrodes ferroelectric Ferroelectric materials Ferroelectricity HZO Integrated circuit interconnections Integrated circuits interconnecting metal Interconnections Iron Residual stress stress effect Tin |
| title | Stress Effects of Interconnecting Metals on Back-End-of-Line Compatible Hf0.5Zr0.5O2 Ferroelectric Capacitors |
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