Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms
DRAM is a key driver of performance and cost in public cloud servers. At the same time, a significant amount of DRAM is underutilized due to fragmented use across servers. Emerging interconnects such as CXL offer a path towards improving utilization through memory pooling. However, the design space...
Gespeichert in:
Veröffentlicht in: | IEEE MICRO 2023-03, Vol.43 (2), p.1-10 |
---|---|
Hauptverfasser: | , , , , , , , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 10 |
---|---|
container_issue | 2 |
container_start_page | 1 |
container_title | IEEE MICRO |
container_volume | 43 |
creator | Berger, Daniel S. Ernst, Daniel Li, Huaicheng Zardoshti, Pantea Shah, Monish Rajadnya, Samir Lee, Scott Hsu, Lisa Agarwal, Ishwar Hill, Mark D. Bianchini, Ricardo |
description | DRAM is a key driver of performance and cost in public cloud servers. At the same time, a significant amount of DRAM is underutilized due to fragmented use across servers. Emerging interconnects such as CXL offer a path towards improving utilization through memory pooling. However, the design space of CXL-based memory systems is large, with key questions around the size, reach, and topology of the memory pool. At the same time, using pools requires navigating complex design constraints around performance, virtualization, and management. This paper discusses why cloud providers should deploy CXL memory pools, key design constraints, and observations in designing towards practical deployment. We identify configuration examples with significant positive return of investment. |
doi_str_mv | 10.1109/MM.2023.3241586 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2784550529</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>10034802</ieee_id><sourcerecordid>2784550529</sourcerecordid><originalsourceid>FETCH-LOGICAL-c331t-cbd3fa2c69f5faa17b8cda03b5b2e33a724bcd8bb3acf8ab590123973eae3b933</originalsourceid><addsrcrecordid>eNpNkD1PwzAQhi0EEqUwszBYYk5r--LaHiGUD6kRHYrEZtmOjVKldbGbof-eVO3AdNLped_TPQjdUzKhlKhpXU8YYTABVlIuZxdoRBWIoqQlXKIRYYIVVAC7Rjc5rwkhnBE5QvMXn9ufLV4l0_gYQsbtFlffi-LZZN_g2m9iOuBljF3GISa87G3XOlx1sW_wsjP7YbnJt-gqmC77u_Mco6_X-ap6Lxafbx_V06JwAHRfONtAMMzNVODBGCqsdI0hYLllHsAIVlrXSGvBuCCN5YpQBkqANx6sAhijx1PvLsXf3ue9Xsc-bYeTmglZcj58pQZqeqJcijknH_QutRuTDpoSfXSl61ofXemzqyHxcEq03vt_NIFSDtwfSkFkiA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2784550529</pqid></control><display><type>article</type><title>Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms</title><source>IEEE Electronic Library (IEL)</source><creator>Berger, Daniel S. ; Ernst, Daniel ; Li, Huaicheng ; Zardoshti, Pantea ; Shah, Monish ; Rajadnya, Samir ; Lee, Scott ; Hsu, Lisa ; Agarwal, Ishwar ; Hill, Mark D. ; Bianchini, Ricardo</creator><creatorcontrib>Berger, Daniel S. ; Ernst, Daniel ; Li, Huaicheng ; Zardoshti, Pantea ; Shah, Monish ; Rajadnya, Samir ; Lee, Scott ; Hsu, Lisa ; Agarwal, Ishwar ; Hill, Mark D. ; Bianchini, Ricardo</creatorcontrib><description>DRAM is a key driver of performance and cost in public cloud servers. At the same time, a significant amount of DRAM is underutilized due to fragmented use across servers. Emerging interconnects such as CXL offer a path towards improving utilization through memory pooling. However, the design space of CXL-based memory systems is large, with key questions around the size, reach, and topology of the memory pool. At the same time, using pools requires navigating complex design constraints around performance, virtualization, and management. This paper discusses why cloud providers should deploy CXL memory pools, key design constraints, and observations in designing towards practical deployment. We identify configuration examples with significant positive return of investment.</description><identifier>ISSN: 0272-1732</identifier><identifier>EISSN: 1937-4143</identifier><identifier>DOI: 10.1109/MM.2023.3241586</identifier><identifier>CODEN: IEMIDZ</identifier><language>eng</language><publisher>Los Alamitos: IEEE</publisher><subject>Bandwidth ; Cloud computing ; Costs ; Dynamic random access memory ; Hardware ; Memory management ; Pools ; Random access memory ; Servers ; Topology</subject><ispartof>IEEE MICRO, 2023-03, Vol.43 (2), p.1-10</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c331t-cbd3fa2c69f5faa17b8cda03b5b2e33a724bcd8bb3acf8ab590123973eae3b933</citedby><cites>FETCH-LOGICAL-c331t-cbd3fa2c69f5faa17b8cda03b5b2e33a724bcd8bb3acf8ab590123973eae3b933</cites><orcidid>0000-0002-3911-1512</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/10034802$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54737</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/10034802$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Berger, Daniel S.</creatorcontrib><creatorcontrib>Ernst, Daniel</creatorcontrib><creatorcontrib>Li, Huaicheng</creatorcontrib><creatorcontrib>Zardoshti, Pantea</creatorcontrib><creatorcontrib>Shah, Monish</creatorcontrib><creatorcontrib>Rajadnya, Samir</creatorcontrib><creatorcontrib>Lee, Scott</creatorcontrib><creatorcontrib>Hsu, Lisa</creatorcontrib><creatorcontrib>Agarwal, Ishwar</creatorcontrib><creatorcontrib>Hill, Mark D.</creatorcontrib><creatorcontrib>Bianchini, Ricardo</creatorcontrib><title>Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms</title><title>IEEE MICRO</title><addtitle>MM</addtitle><description>DRAM is a key driver of performance and cost in public cloud servers. At the same time, a significant amount of DRAM is underutilized due to fragmented use across servers. Emerging interconnects such as CXL offer a path towards improving utilization through memory pooling. However, the design space of CXL-based memory systems is large, with key questions around the size, reach, and topology of the memory pool. At the same time, using pools requires navigating complex design constraints around performance, virtualization, and management. This paper discusses why cloud providers should deploy CXL memory pools, key design constraints, and observations in designing towards practical deployment. We identify configuration examples with significant positive return of investment.</description><subject>Bandwidth</subject><subject>Cloud computing</subject><subject>Costs</subject><subject>Dynamic random access memory</subject><subject>Hardware</subject><subject>Memory management</subject><subject>Pools</subject><subject>Random access memory</subject><subject>Servers</subject><subject>Topology</subject><issn>0272-1732</issn><issn>1937-4143</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkD1PwzAQhi0EEqUwszBYYk5r--LaHiGUD6kRHYrEZtmOjVKldbGbof-eVO3AdNLped_TPQjdUzKhlKhpXU8YYTABVlIuZxdoRBWIoqQlXKIRYYIVVAC7Rjc5rwkhnBE5QvMXn9ufLV4l0_gYQsbtFlffi-LZZN_g2m9iOuBljF3GISa87G3XOlx1sW_wsjP7YbnJt-gqmC77u_Mco6_X-ap6Lxafbx_V06JwAHRfONtAMMzNVODBGCqsdI0hYLllHsAIVlrXSGvBuCCN5YpQBkqANx6sAhijx1PvLsXf3ue9Xsc-bYeTmglZcj58pQZqeqJcijknH_QutRuTDpoSfXSl61ofXemzqyHxcEq03vt_NIFSDtwfSkFkiA</recordid><startdate>20230301</startdate><enddate>20230301</enddate><creator>Berger, Daniel S.</creator><creator>Ernst, Daniel</creator><creator>Li, Huaicheng</creator><creator>Zardoshti, Pantea</creator><creator>Shah, Monish</creator><creator>Rajadnya, Samir</creator><creator>Lee, Scott</creator><creator>Hsu, Lisa</creator><creator>Agarwal, Ishwar</creator><creator>Hill, Mark D.</creator><creator>Bianchini, Ricardo</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><orcidid>https://orcid.org/0000-0002-3911-1512</orcidid></search><sort><creationdate>20230301</creationdate><title>Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms</title><author>Berger, Daniel S. ; Ernst, Daniel ; Li, Huaicheng ; Zardoshti, Pantea ; Shah, Monish ; Rajadnya, Samir ; Lee, Scott ; Hsu, Lisa ; Agarwal, Ishwar ; Hill, Mark D. ; Bianchini, Ricardo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c331t-cbd3fa2c69f5faa17b8cda03b5b2e33a724bcd8bb3acf8ab590123973eae3b933</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2023</creationdate><topic>Bandwidth</topic><topic>Cloud computing</topic><topic>Costs</topic><topic>Dynamic random access memory</topic><topic>Hardware</topic><topic>Memory management</topic><topic>Pools</topic><topic>Random access memory</topic><topic>Servers</topic><topic>Topology</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Berger, Daniel S.</creatorcontrib><creatorcontrib>Ernst, Daniel</creatorcontrib><creatorcontrib>Li, Huaicheng</creatorcontrib><creatorcontrib>Zardoshti, Pantea</creatorcontrib><creatorcontrib>Shah, Monish</creatorcontrib><creatorcontrib>Rajadnya, Samir</creatorcontrib><creatorcontrib>Lee, Scott</creatorcontrib><creatorcontrib>Hsu, Lisa</creatorcontrib><creatorcontrib>Agarwal, Ishwar</creatorcontrib><creatorcontrib>Hill, Mark D.</creatorcontrib><creatorcontrib>Bianchini, Ricardo</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE MICRO</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Berger, Daniel S.</au><au>Ernst, Daniel</au><au>Li, Huaicheng</au><au>Zardoshti, Pantea</au><au>Shah, Monish</au><au>Rajadnya, Samir</au><au>Lee, Scott</au><au>Hsu, Lisa</au><au>Agarwal, Ishwar</au><au>Hill, Mark D.</au><au>Bianchini, Ricardo</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms</atitle><jtitle>IEEE MICRO</jtitle><stitle>MM</stitle><date>2023-03-01</date><risdate>2023</risdate><volume>43</volume><issue>2</issue><spage>1</spage><epage>10</epage><pages>1-10</pages><issn>0272-1732</issn><eissn>1937-4143</eissn><coden>IEMIDZ</coden><abstract>DRAM is a key driver of performance and cost in public cloud servers. At the same time, a significant amount of DRAM is underutilized due to fragmented use across servers. Emerging interconnects such as CXL offer a path towards improving utilization through memory pooling. However, the design space of CXL-based memory systems is large, with key questions around the size, reach, and topology of the memory pool. At the same time, using pools requires navigating complex design constraints around performance, virtualization, and management. This paper discusses why cloud providers should deploy CXL memory pools, key design constraints, and observations in designing towards practical deployment. We identify configuration examples with significant positive return of investment.</abstract><cop>Los Alamitos</cop><pub>IEEE</pub><doi>10.1109/MM.2023.3241586</doi><tpages>10</tpages><orcidid>https://orcid.org/0000-0002-3911-1512</orcidid><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0272-1732 |
ispartof | IEEE MICRO, 2023-03, Vol.43 (2), p.1-10 |
issn | 0272-1732 1937-4143 |
language | eng |
recordid | cdi_proquest_journals_2784550529 |
source | IEEE Electronic Library (IEL) |
subjects | Bandwidth Cloud computing Costs Dynamic random access memory Hardware Memory management Pools Random access memory Servers Topology |
title | Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T06%3A00%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Design%20Tradeoffs%20in%20CXL-Based%20Memory%20Pools%20for%20Public%20Cloud%20Platforms&rft.jtitle=IEEE%20MICRO&rft.au=Berger,%20Daniel%20S.&rft.date=2023-03-01&rft.volume=43&rft.issue=2&rft.spage=1&rft.epage=10&rft.pages=1-10&rft.issn=0272-1732&rft.eissn=1937-4143&rft.coden=IEMIDZ&rft_id=info:doi/10.1109/MM.2023.3241586&rft_dat=%3Cproquest_RIE%3E2784550529%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2784550529&rft_id=info:pmid/&rft_ieee_id=10034802&rfr_iscdi=true |