Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Random Access Memory (RAM) refers to the main memory of a computer. For the central processor unit (CPU) to operate quickly and effectively, it stores operating system software, applications, and other data. Unfortunately, single event upset and other high-soft error problems plague standard static RAM (SRAMs) in aircraft applications (SEU). Many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD), such as the 12T We-Quatro and twelve-transistor (12T) Dice SRAM cells, have been created to address the soft error issues. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 × 32 array architecture. The power consumption of a 32 × 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 × 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology file is used to simulate the comparative analysis for the SRAM cell.