Structured Term Pruning for Computational Efficient Neural Networks Inference
The state-of-the-art convolutional neural network accelerators are showing a growing interest in exploiting the bit-level sparsity and eliminating the ineffectual computations of zero bits. However, the excessive redundancy and the irregular distribution of nonzero bits limit the real speedup in the...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2023-01, Vol.42 (1), p.190-203 |
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creator | Huang, Kai Li, Bowen Chen, Siang Claesen, Luc Xi, Wei Chen, Junjian Jiang, Xiaowen Liu, Zhili Xiong, Dongliang Yan, Xiaolang |
description | The state-of-the-art convolutional neural network accelerators are showing a growing interest in exploiting the bit-level sparsity and eliminating the ineffectual computations of zero bits. However, the excessive redundancy and the irregular distribution of nonzero bits limit the real speedup in the accelerators. To address this, we propose an algorithm-architecture codesign, named structured term pruning (STP), to boost the computation efficiency of neural networks inference. Specifically, we enhance the bit sparsity by guiding the weights toward the value with fewer power-of-two terms. Then, we structure the terms with layer-wise group budgets. Retraining is adopted to recover the accuracy drop. We also design the hardware of the group processing element and the fast signed-digital encoder for efficient implementation of STP networks. The system design of STP is realized with some easy alterations on an input stationary systolic array design. Extensive evaluation results demonstrate that STP can reduce significant inference computation costs, and achieve 2.35\times computational energy saving for the ResNet18 network on the ImageNet dataset. |
doi_str_mv | 10.1109/TCAD.2022.3168506 |
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However, the excessive redundancy and the irregular distribution of nonzero bits limit the real speedup in the accelerators. To address this, we propose an algorithm-architecture codesign, named structured term pruning (STP), to boost the computation efficiency of neural networks inference. Specifically, we enhance the bit sparsity by guiding the weights toward the value with fewer power-of-two terms. Then, we structure the terms with layer-wise group budgets. Retraining is adopted to recover the accuracy drop. We also design the hardware of the group processing element and the fast signed-digital encoder for efficient implementation of STP networks. The system design of STP is realized with some easy alterations on an input stationary systolic array design. Extensive evaluation results demonstrate that STP can reduce significant inference computation costs, and achieve <inline-formula> <tex-math notation="LaTeX">2.35\times </tex-math></inline-formula> computational energy saving for the ResNet18 network on the ImageNet dataset.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2022.3168506</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Accelerators ; Algorithm-architecture codesign ; Algorithms ; Artificial neural networks ; Biological neural networks ; Co-design ; Coders ; compression and acceleration ; Computational efficiency ; Encoding ; Hardware ; Inference ; Neural networks ; quantization ; Quantization (signal) ; Redundancy ; Sparsity ; Systems design ; systolic array (SA) ; Systolic arrays ; Training</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.190-203</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2023</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-a6c1b8260887786926fd4c1c3ef93eb3d349a5a5731307e90b8267ad572037c43</citedby><cites>FETCH-LOGICAL-c293t-a6c1b8260887786926fd4c1c3ef93eb3d349a5a5731307e90b8267ad572037c43</cites><orcidid>0000-0003-0405-6290 ; 0000-0002-6283-2262 ; 0000-0002-9061-7754 ; 0000-0003-2846-781X ; 0000-0001-7525-9672</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9759473$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9759473$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Huang, Kai</creatorcontrib><creatorcontrib>Li, Bowen</creatorcontrib><creatorcontrib>Chen, Siang</creatorcontrib><creatorcontrib>Claesen, Luc</creatorcontrib><creatorcontrib>Xi, Wei</creatorcontrib><creatorcontrib>Chen, Junjian</creatorcontrib><creatorcontrib>Jiang, Xiaowen</creatorcontrib><creatorcontrib>Liu, Zhili</creatorcontrib><creatorcontrib>Xiong, Dongliang</creatorcontrib><creatorcontrib>Yan, Xiaolang</creatorcontrib><title>Structured Term Pruning for Computational Efficient Neural Networks Inference</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>The state-of-the-art convolutional neural network accelerators are showing a growing interest in exploiting the bit-level sparsity and eliminating the ineffectual computations of zero bits. However, the excessive redundancy and the irregular distribution of nonzero bits limit the real speedup in the accelerators. To address this, we propose an algorithm-architecture codesign, named structured term pruning (STP), to boost the computation efficiency of neural networks inference. Specifically, we enhance the bit sparsity by guiding the weights toward the value with fewer power-of-two terms. Then, we structure the terms with layer-wise group budgets. Retraining is adopted to recover the accuracy drop. We also design the hardware of the group processing element and the fast signed-digital encoder for efficient implementation of STP networks. The system design of STP is realized with some easy alterations on an input stationary systolic array design. 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subjects | Accelerators Algorithm-architecture codesign Algorithms Artificial neural networks Biological neural networks Co-design Coders compression and acceleration Computational efficiency Encoding Hardware Inference Neural networks quantization Quantization (signal) Redundancy Sparsity Systems design systolic array (SA) Systolic arrays Training |
title | Structured Term Pruning for Computational Efficient Neural Networks Inference |
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