PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning
Recently, the topic of how to utilize prior knowledge obtained by machine-learning (ML) techniques during the EDA flow has been widely studied. In this article, we study this topic and propose a practical plug-in named PROS for both routability optimization and routed wirelength estimation which can...
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Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2023-01, Vol.42 (1), p.164-177 |
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creator | Chen, Jingsong Kuang, Jian Zhao, Guowei Huang, Dennis J.-H. Young, Evangeline F. Y. |
description | Recently, the topic of how to utilize prior knowledge obtained by machine-learning (ML) techniques during the EDA flow has been widely studied. In this article, we study this topic and propose a practical plug-in named PROS for both routability optimization and routed wirelength estimation which can be applied in the state-of-the-art commercial EDA tool or an academic EDA flow with negligible runtime overhead. PROS consists of three parts: 1) an effective fully convolutional network (FCN)-based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion; 2) a parameter optimizer that can reasonably adjust GR cost parameters based on the prediction result to generate a better GR solution for detailed routing (DR); and 3) a convolutional neural network (CNN)-based wirelength estimator which can report accurate routed wirelength at the placement stage by using the predicted GR congestion. Experiments show that on the industrial benchmark suite in the advanced technology node, PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average, and on the DAC-2012 benchmark suite, PROS can achieve a very low error rate (1.82%) for wirelength estimation which greatly outperforms that of FLUTE (21.52%) by 19.70%. |
doi_str_mv | 10.1109/TCAD.2022.3168259 |
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PROS consists of three parts: 1) an effective fully convolutional network (FCN)-based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion; 2) a parameter optimizer that can reasonably adjust GR cost parameters based on the prediction result to generate a better GR solution for detailed routing (DR); and 3) a convolutional neural network (CNN)-based wirelength estimator which can report accurate routed wirelength at the placement stage by using the predicted GR congestion. Experiments show that on the industrial benchmark suite in the advanced technology node, PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average, and on the DAC-2012 benchmark suite, PROS can achieve a very low error rate (1.82%) for wirelength estimation which greatly outperforms that of FLUTE (21.52%) by 19.70%.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2022.3168259</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Artificial neural networks ; Benchmark testing ; Benchmarks ; Circuit optimization ; Congestion ; Costs ; Deep learning ; design automation ; Estimation ; Machine learning ; Optimization ; Parameters ; Placement ; Plugs ; Routing ; Runtime ; Wires</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2023-01, Vol.42 (1), p.164-177</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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Y.</creatorcontrib><title>PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>Recently, the topic of how to utilize prior knowledge obtained by machine-learning (ML) techniques during the EDA flow has been widely studied. In this article, we study this topic and propose a practical plug-in named PROS for both routability optimization and routed wirelength estimation which can be applied in the state-of-the-art commercial EDA tool or an academic EDA flow with negligible runtime overhead. PROS consists of three parts: 1) an effective fully convolutional network (FCN)-based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion; 2) a parameter optimizer that can reasonably adjust GR cost parameters based on the prediction result to generate a better GR solution for detailed routing (DR); and 3) a convolutional neural network (CNN)-based wirelength estimator which can report accurate routed wirelength at the placement stage by using the predicted GR congestion. Experiments show that on the industrial benchmark suite in the advanced technology node, PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average, and on the DAC-2012 benchmark suite, PROS can achieve a very low error rate (1.82%) for wirelength estimation which greatly outperforms that of FLUTE (21.52%) by 19.70%.</description><subject>Artificial neural networks</subject><subject>Benchmark testing</subject><subject>Benchmarks</subject><subject>Circuit optimization</subject><subject>Congestion</subject><subject>Costs</subject><subject>Deep learning</subject><subject>design automation</subject><subject>Estimation</subject><subject>Machine learning</subject><subject>Optimization</subject><subject>Parameters</subject><subject>Placement</subject><subject>Plugs</subject><subject>Routing</subject><subject>Runtime</subject><subject>Wires</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2023</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFZ_gHhZ8Jw4-5H98FbaqoVCS23xuKTJpKbEpG6SQ_31pqZ4GoZ53pnhIeSeQcgY2Kf1eDQJOXAeCqYMj-wFGTArdCBZxC7JALg2AYCGa3JT13sAJiNuBwSXq8U75SE80xFdFu0umJU0qzxdVW0Tb_Mib450cWjyr_wnbvKqpHGZ_g0xpR-5xwLLXfNJp3WH9MCmzssdnSAe6BxjX3bdLbnK4qLGu3Mdks3LdD1-C-aL19l4NA8SbkUTpKgBk0ylIhZagAGljESuIp2wOFWWC9Bc2W0mE51thTGpSVPJEDVPZGSUGJLHfu_BV98t1o3bV60vu5OO60hFCpSAjmI9lfiqrj1m7uC75_3RMXAnm-5k051surPNLvPQZ3JE_OetjqxUUvwCUCZvHQ</recordid><startdate>202301</startdate><enddate>202301</enddate><creator>Chen, Jingsong</creator><creator>Kuang, Jian</creator><creator>Zhao, Guowei</creator><creator>Huang, Dennis J.-H.</creator><creator>Young, Evangeline F. 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Y.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Jingsong</au><au>Kuang, Jian</au><au>Zhao, Guowei</au><au>Huang, Dennis J.-H.</au><au>Young, Evangeline F. Y.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2023-01</date><risdate>2023</risdate><volume>42</volume><issue>1</issue><spage>164</spage><epage>177</epage><pages>164-177</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>Recently, the topic of how to utilize prior knowledge obtained by machine-learning (ML) techniques during the EDA flow has been widely studied. In this article, we study this topic and propose a practical plug-in named PROS for both routability optimization and routed wirelength estimation which can be applied in the state-of-the-art commercial EDA tool or an academic EDA flow with negligible runtime overhead. PROS consists of three parts: 1) an effective fully convolutional network (FCN)-based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion; 2) a parameter optimizer that can reasonably adjust GR cost parameters based on the prediction result to generate a better GR solution for detailed routing (DR); and 3) a convolutional neural network (CNN)-based wirelength estimator which can report accurate routed wirelength at the placement stage by using the predicted GR congestion. Experiments show that on the industrial benchmark suite in the advanced technology node, PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average, and on the DAC-2012 benchmark suite, PROS can achieve a very low error rate (1.82%) for wirelength estimation which greatly outperforms that of FLUTE (21.52%) by 19.70%.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2022.3168259</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0001-9867-9805</orcidid></addata></record> |
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subjects | Artificial neural networks Benchmark testing Benchmarks Circuit optimization Congestion Costs Deep learning design automation Estimation Machine learning Optimization Parameters Placement Plugs Routing Runtime Wires |
title | PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning |
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