Endurance of 2 Mbit Based BEOL Integrated ReRAM

In this work, we experimentally characterize the endurance of 2 Mbit resistive switching random access memories (ReRAMs) from a 16 MBit test-chip. Here, very rare failure events where the memory cells become stuck in the low-resistive state (LRS) are observed. As this failure mechanism is the limiti...

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Veröffentlicht in:	IEEE access 2022, Vol.10, p.122696-122705
Hauptverfasser:	Kopperberg, Nils, Wiefels, Stefan, Hofmann, Karl, Otterstedt, Jan, Wouters, Dirk J., Waser, Rainer, Menzel, Stephan
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Computer simulation Endurance Failure analysis Failure mechanisms KMC Limiting OxRAM Programming Random access memory ReRAM RESET failure Resistance stuck at SET Switches Switching theory Transistors VCM Voltage control Voltage dividers
Online-Zugang:	Volltext
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