A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration
A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler a...
Gespeichert in:
Veröffentlicht in: | IEEE journal of solid-state circuits 2022-11, Vol.57 (11), p.3336-3347 |
---|---|
Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 3347 |
---|---|
container_issue | 11 |
container_start_page | 3336 |
container_title | IEEE journal of solid-state circuits |
container_volume | 57 |
creator | Choi, Kyung-Sik Kim, Keun-Mok Ko, Jinho Lee, Sang-Gug |
description | A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- {Q} . Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 \mu \text{W} in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%. |
doi_str_mv | 10.1109/JSSC.2022.3172467 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_journals_2727045266</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>9773282</ieee_id><sourcerecordid>2727045266</sourcerecordid><originalsourceid>FETCH-LOGICAL-c223t-216c5ad6112e0509d639360f7d02826db37bf65344b083daf88c4bd504a2db343</originalsourceid><addsrcrecordid>eNo9kE9PAjEQxRujiYh-AOOlieeF_tt290hWEAxGEzDx1nR3u1gsu9iWw_rpLYF4msy8NzMvPwDuMRphjPLxy2pVjAgiZESxIIyLCzDAaZolWNDPSzBACGdJThC6Bjfeb2PLWIYH4HsCc5zC1_kvXHRruHaq9TsTgnZwutvbrjftBs6c_jnotuqjbvY2aqqt4ZPZmKCs7WHRtcF11uo4PIQ-KfrK6vH7l_IaFsqa0qlguvYWXDXKen13rkPwMZuui3myfHteFJNlUhFCQ0Iwr1JVc4yJRinKa05zylEjakQywuuSirLhKWWsRBmtVZNlFSvrFDFFosjoEDye7u5dF3P7ILfdwbXxpSSCCMRSwnl04ZOrcp33Tjdy78xOuV5iJI9M5ZGpPDKVZ6Zx5-G0Y7TW__5cCBqT0T8G2XG2</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2727045266</pqid></control><display><type>article</type><title>A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration</title><source>IEEE Xplore</source><creator>Choi, Kyung-Sik ; Kim, Keun-Mok ; Ko, Jinho ; Lee, Sang-Gug</creator><creatorcontrib>Choi, Kyung-Sik ; Kim, Keun-Mok ; Ko, Jinho ; Lee, Sang-Gug</creatorcontrib><description><![CDATA[A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low-<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2022.3172467</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Binary frequency-shift keying (BFSK) ; Calibration ; Circuit design ; class-D ; CMOS ; duty-cycle calibration ; Frequency shift keying ; Frequency synthesizers ; Harmonic distortion ; High pass filters ; Internet of Things ; Internet-of-Things (IoT) ; Keying ; low-power ; Phase locked loops ; power amplifier (PA) ; Power amplifiers ; Power demand ; Stability analysis ; transmitter (TX) ; Transmitters ; Voltage-controlled oscillators</subject><ispartof>IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.3336-3347</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c223t-216c5ad6112e0509d639360f7d02826db37bf65344b083daf88c4bd504a2db343</citedby><cites>FETCH-LOGICAL-c223t-216c5ad6112e0509d639360f7d02826db37bf65344b083daf88c4bd504a2db343</cites><orcidid>0000-0003-0040-3558 ; 0000-0002-6154-8470 ; 0000-0001-8074-4090 ; 0000-0002-0632-2188</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9773282$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9773282$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Choi, Kyung-Sik</creatorcontrib><creatorcontrib>Kim, Keun-Mok</creatorcontrib><creatorcontrib>Ko, Jinho</creatorcontrib><creatorcontrib>Lee, Sang-Gug</creatorcontrib><title>A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low-<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.]]></description><subject>Binary frequency-shift keying (BFSK)</subject><subject>Calibration</subject><subject>Circuit design</subject><subject>class-D</subject><subject>CMOS</subject><subject>duty-cycle calibration</subject><subject>Frequency shift keying</subject><subject>Frequency synthesizers</subject><subject>Harmonic distortion</subject><subject>High pass filters</subject><subject>Internet of Things</subject><subject>Internet-of-Things (IoT)</subject><subject>Keying</subject><subject>low-power</subject><subject>Phase locked loops</subject><subject>power amplifier (PA)</subject><subject>Power amplifiers</subject><subject>Power demand</subject><subject>Stability analysis</subject><subject>transmitter (TX)</subject><subject>Transmitters</subject><subject>Voltage-controlled oscillators</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE9PAjEQxRujiYh-AOOlieeF_tt290hWEAxGEzDx1nR3u1gsu9iWw_rpLYF4msy8NzMvPwDuMRphjPLxy2pVjAgiZESxIIyLCzDAaZolWNDPSzBACGdJThC6Bjfeb2PLWIYH4HsCc5zC1_kvXHRruHaq9TsTgnZwutvbrjftBs6c_jnotuqjbvY2aqqt4ZPZmKCs7WHRtcF11uo4PIQ-KfrK6vH7l_IaFsqa0qlguvYWXDXKen13rkPwMZuui3myfHteFJNlUhFCQ0Iwr1JVc4yJRinKa05zylEjakQywuuSirLhKWWsRBmtVZNlFSvrFDFFosjoEDye7u5dF3P7ILfdwbXxpSSCCMRSwnl04ZOrcp33Tjdy78xOuV5iJI9M5ZGpPDKVZ6Zx5-G0Y7TW__5cCBqT0T8G2XG2</recordid><startdate>20221101</startdate><enddate>20221101</enddate><creator>Choi, Kyung-Sik</creator><creator>Kim, Keun-Mok</creator><creator>Ko, Jinho</creator><creator>Lee, Sang-Gug</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-0040-3558</orcidid><orcidid>https://orcid.org/0000-0002-6154-8470</orcidid><orcidid>https://orcid.org/0000-0001-8074-4090</orcidid><orcidid>https://orcid.org/0000-0002-0632-2188</orcidid></search><sort><creationdate>20221101</creationdate><title>A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration</title><author>Choi, Kyung-Sik ; Kim, Keun-Mok ; Ko, Jinho ; Lee, Sang-Gug</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c223t-216c5ad6112e0509d639360f7d02826db37bf65344b083daf88c4bd504a2db343</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Binary frequency-shift keying (BFSK)</topic><topic>Calibration</topic><topic>Circuit design</topic><topic>class-D</topic><topic>CMOS</topic><topic>duty-cycle calibration</topic><topic>Frequency shift keying</topic><topic>Frequency synthesizers</topic><topic>Harmonic distortion</topic><topic>High pass filters</topic><topic>Internet of Things</topic><topic>Internet-of-Things (IoT)</topic><topic>Keying</topic><topic>low-power</topic><topic>Phase locked loops</topic><topic>power amplifier (PA)</topic><topic>Power amplifiers</topic><topic>Power demand</topic><topic>Stability analysis</topic><topic>transmitter (TX)</topic><topic>Transmitters</topic><topic>Voltage-controlled oscillators</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Choi, Kyung-Sik</creatorcontrib><creatorcontrib>Kim, Keun-Mok</creatorcontrib><creatorcontrib>Ko, Jinho</creatorcontrib><creatorcontrib>Lee, Sang-Gug</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Choi, Kyung-Sik</au><au>Kim, Keun-Mok</au><au>Ko, Jinho</au><au>Lee, Sang-Gug</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2022-11-01</date><risdate>2022</risdate><volume>57</volume><issue>11</issue><spage>3336</spage><epage>3347</epage><pages>3336-3347</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract><![CDATA[A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low-<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2022.3172467</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-0040-3558</orcidid><orcidid>https://orcid.org/0000-0002-6154-8470</orcidid><orcidid>https://orcid.org/0000-0001-8074-4090</orcidid><orcidid>https://orcid.org/0000-0002-0632-2188</orcidid></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0018-9200 |
ispartof | IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.3336-3347 |
issn | 0018-9200 1558-173X |
language | eng |
recordid | cdi_proquest_journals_2727045266 |
source | IEEE Xplore |
subjects | Binary frequency-shift keying (BFSK) Calibration Circuit design class-D CMOS duty-cycle calibration Frequency shift keying Frequency synthesizers Harmonic distortion High pass filters Internet of Things Internet-of-Things (IoT) Keying low-power Phase locked loops power amplifier (PA) Power amplifiers Power demand Stability analysis transmitter (TX) Transmitters Voltage-controlled oscillators |
title | A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T00%3A07%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20915%20MHz%20IoT%20Transmitter%20Employing%20Frequency%20Tripler%20and%20Digitally%20Controlled%20Duty-Cycle/Phase%20Calibration&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Choi,%20Kyung-Sik&rft.date=2022-11-01&rft.volume=57&rft.issue=11&rft.spage=3336&rft.epage=3347&rft.pages=3336-3347&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2022.3172467&rft_dat=%3Cproquest_RIE%3E2727045266%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2727045266&rft_id=info:pmid/&rft_ieee_id=9773282&rfr_iscdi=true |