A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration

A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler a...

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Veröffentlicht in:IEEE journal of solid-state circuits 2022-11, Vol.57 (11), p.3336-3347
Hauptverfasser: Choi, Kyung-Sik, Kim, Keun-Mok, Ko, Jinho, Lee, Sang-Gug
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container_issue 11
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creator Choi, Kyung-Sik
Kim, Keun-Mok
Ko, Jinho
Lee, Sang-Gug
description A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- {Q} . Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 \mu \text{W} in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.
doi_str_mv 10.1109/JSSC.2022.3172467
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The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low-<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. 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The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low-<inline-formula> <tex-math notation="LaTeX">{Q} </tex-math></inline-formula>. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902-928 MHz while dissipating 210 <inline-formula> <tex-math notation="LaTeX">\mu \text{W} </tex-math></inline-formula> in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2022.3172467</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-0040-3558</orcidid><orcidid>https://orcid.org/0000-0002-6154-8470</orcidid><orcidid>https://orcid.org/0000-0001-8074-4090</orcidid><orcidid>https://orcid.org/0000-0002-0632-2188</orcidid></addata></record>
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ispartof IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.3336-3347
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subjects Binary frequency-shift keying (BFSK)
Calibration
Circuit design
class-D
CMOS
duty-cycle calibration
Frequency shift keying
Frequency synthesizers
Harmonic distortion
High pass filters
Internet of Things
Internet-of-Things (IoT)
Keying
low-power
Phase locked loops
power amplifier (PA)
Power amplifiers
Power demand
Stability analysis
transmitter (TX)
Transmitters
Voltage-controlled oscillators
title A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration
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