Design and implementation of power efficient clock gated dual-port SRAM

Synchronous clock gated Dual-port RAM has been designed in this paper. To increase the design’s power, a negative latch-based clock gating approach was used. On Xilinx Vivado ML Edition, the design was implemented on an XC7Z010ICLG225-1L device with a - 1-speed grade and the Zynq-7000 FPGA family. The Verilog HDL was used to create the design. A 2-bit AND gate is used to realize clock gating which takes the clock and enable signal as input thus clock become only high when enable is high which reduces the switching frequency and thus power consumption by the clock is reduced as power is directly proportional to (frequency) 2 . Apart from clock gating, the SRAM is Dual-Port based, allowing multiple reads or writes to occur simultaneously, or at approximately the same time, unlike single-port RAM, which permits only one access at a given time. The power consumption value of the clock signal with clock gating at 100 GHz is 627.61 mW as compared to power consumption without clock gating which is 1405 mW, at a clock frequency of 100 GHz, a 55 percent reduction in total clock power was achieved. Xilinx Vivado ML Edition’s XPower Analyzer tool was used to calculate the device’s power.