35 dB Harmonics Rejection Over 20 GHz Bandwidth in 55 nm BiCMOS

A frequency multiplier by six (sextupler) for local oscillation (LO) generation in [Formula Omitted]-band is presented. It comprises a tripler, a doubler, and an output buffer. A detailed analysis is proposed to discuss the optimal order of the multiplication stages to minimize the unwanted harmonics of the input. Moreover, novel circuit topologies for the tripler and doubler are introduced. The tripler core is devised to reproduce the transcharacteristic of a third-order polynomial that ideally generates only the third harmonic of a sinusoidal input signal. By leveraging an envelope detector for adaptive biasing, the circuit maintains excellent suppression of the driving signal and unwanted harmonics over wide variations of the input power. The proposed topology improves output signal purity and current conversion efficiency against classical triplers based on the transistors biased in class C. The cascaded frequency doubler is based on a novel push–push configuration that provides a differential output and excellent odd-order harmonic rejection due to an enhanced robustness to amplitude and phase unbalances of the driving signal. The sextupler is fabricated in a 55-nm SiGe-BiCMOS technology. Driven with a 0-dBm input signal and consuming 63.1 mW of dc power, it delivers [Formula Omitted] up to 5.6 dBm at 72 GHz. [Formula Omitted] is above 0 dBm over 20-GHz bandwidth (BW), while undesired harmonics of the input are suppressed by more than 35 dB. Compared to previously reported millimeter-wave frequency multipliers, the sextupler demonstrates improved harmonic rejection, conversion gain, and efficiency, without compromising the operation BW and output power.