Low-Power Hardware Design of Binary Arithmetic Encoder in H.264
Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC....
Gespeichert in:
| Veröffentlicht in: | International journal of advanced computer science & applications 2017-01, Vol.8 (7) |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | 7 |
| container_start_page | |
| container_title | International journal of advanced computer science & applications |
| container_volume | 8 |
| creator | Hamida, Ben Jarray, Nedra Abdelkrim, Zitouni |
| description | Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications. |
| doi_str_mv | 10.14569/IJACSA.2017.080756 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2656439828</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2656439828</sourcerecordid><originalsourceid>FETCH-LOGICAL-c202t-83e3cf800b022d8abdf1c37bd3854891070d84a547c97ef57224c9f82e4776943</originalsourceid><addsrcrecordid>eNotkE1Lw0AQhhdRsNT-Ai8LnhP3--MksVZTKSio4G1JNruaYrN1NyX4742Nc5k5PMzM-wBwiVGOGRf6ev1YLF-KnCAsc6SQ5OIEzAjmIuNcotPjrDKM5Ps5WKS0RWNRTYSiM3CzCUP2HAYXYVnFZqiig3cutR8dDB7etl0Vf2AR2_5z5_rWwlVnQzPCbQfLnAh2Ac589ZXc4r_Pwdv96nVZZpunh_Wy2GSWINJnijpqvUKoRoQ0qqobjy2VdUMVZ0qPv6FGsYozabV0nktCmNVeEcekFJrRObia9u5j-D641JttOMRuPGmI4IJRrYgaKTpRNoaUovNmH9vdGMFgZI6yzCTL_Mkykyz6C3xjWc4</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2656439828</pqid></control><display><type>article</type><title>Low-Power Hardware Design of Binary Arithmetic Encoder in H.264</title><source>Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals</source><creator>Hamida, Ben ; Jarray, Nedra ; Abdelkrim, Zitouni</creator><creatorcontrib>Hamida, Ben ; Jarray, Nedra ; Abdelkrim, Zitouni</creatorcontrib><description>Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications.</description><identifier>ISSN: 2158-107X</identifier><identifier>EISSN: 2156-5570</identifier><identifier>DOI: 10.14569/IJACSA.2017.080756</identifier><language>eng</language><publisher>West Yorkshire: Science and Information (SAI) Organization Limited</publisher><subject>Algorithms ; Arithmetic coding ; Binary codes ; Coders ; Computer science ; Digital signal processors ; Hardware ; Power consumption ; Software</subject><ispartof>International journal of advanced computer science & applications, 2017-01, Vol.8 (7)</ispartof><rights>2017. This work is licensed under https://creativecommons.org/licenses/by/4.0/ (the “License”). Notwithstanding the ProQuest Terms and Conditions, you may use this content in accordance with the terms of the License.</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Hamida, Ben</creatorcontrib><creatorcontrib>Jarray, Nedra</creatorcontrib><creatorcontrib>Abdelkrim, Zitouni</creatorcontrib><title>Low-Power Hardware Design of Binary Arithmetic Encoder in H.264</title><title>International journal of advanced computer science & applications</title><description>Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications.</description><subject>Algorithms</subject><subject>Arithmetic coding</subject><subject>Binary codes</subject><subject>Coders</subject><subject>Computer science</subject><subject>Digital signal processors</subject><subject>Hardware</subject><subject>Power consumption</subject><subject>Software</subject><issn>2158-107X</issn><issn>2156-5570</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>8G5</sourceid><sourceid>BENPR</sourceid><sourceid>GUQSH</sourceid><sourceid>M2O</sourceid><recordid>eNotkE1Lw0AQhhdRsNT-Ai8LnhP3--MksVZTKSio4G1JNruaYrN1NyX4742Nc5k5PMzM-wBwiVGOGRf6ev1YLF-KnCAsc6SQ5OIEzAjmIuNcotPjrDKM5Ps5WKS0RWNRTYSiM3CzCUP2HAYXYVnFZqiig3cutR8dDB7etl0Vf2AR2_5z5_rWwlVnQzPCbQfLnAh2Ac589ZXc4r_Pwdv96nVZZpunh_Wy2GSWINJnijpqvUKoRoQ0qqobjy2VdUMVZ0qPv6FGsYozabV0nktCmNVeEcekFJrRObia9u5j-D641JttOMRuPGmI4IJRrYgaKTpRNoaUovNmH9vdGMFgZI6yzCTL_Mkykyz6C3xjWc4</recordid><startdate>20170101</startdate><enddate>20170101</enddate><creator>Hamida, Ben</creator><creator>Jarray, Nedra</creator><creator>Abdelkrim, Zitouni</creator><general>Science and Information (SAI) Organization Limited</general><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7XB</scope><scope>8FE</scope><scope>8FG</scope><scope>8FK</scope><scope>8G5</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>GNUQQ</scope><scope>GUQSH</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>M2O</scope><scope>MBDVC</scope><scope>P5Z</scope><scope>P62</scope><scope>PIMPY</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>Q9U</scope></search><sort><creationdate>20170101</creationdate><title>Low-Power Hardware Design of Binary Arithmetic Encoder in H.264</title><author>Hamida, Ben ; Jarray, Nedra ; Abdelkrim, Zitouni</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c202t-83e3cf800b022d8abdf1c37bd3854891070d84a547c97ef57224c9f82e4776943</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Algorithms</topic><topic>Arithmetic coding</topic><topic>Binary codes</topic><topic>Coders</topic><topic>Computer science</topic><topic>Digital signal processors</topic><topic>Hardware</topic><topic>Power consumption</topic><topic>Software</topic><toplevel>online_resources</toplevel><creatorcontrib>Hamida, Ben</creatorcontrib><creatorcontrib>Jarray, Nedra</creatorcontrib><creatorcontrib>Abdelkrim, Zitouni</creatorcontrib><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>Research Library (Alumni Edition)</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>Research Library Prep</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>Research Library</collection><collection>Research Library (Corporate)</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>Publicly Available Content Database</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>ProQuest Central Basic</collection><jtitle>International journal of advanced computer science & applications</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Hamida, Ben</au><au>Jarray, Nedra</au><au>Abdelkrim, Zitouni</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Low-Power Hardware Design of Binary Arithmetic Encoder in H.264</atitle><jtitle>International journal of advanced computer science & applications</jtitle><date>2017-01-01</date><risdate>2017</risdate><volume>8</volume><issue>7</issue><issn>2158-107X</issn><eissn>2156-5570</eissn><abstract>Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications.</abstract><cop>West Yorkshire</cop><pub>Science and Information (SAI) Organization Limited</pub><doi>10.14569/IJACSA.2017.080756</doi><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 2158-107X |
| ispartof | International journal of advanced computer science & applications, 2017-01, Vol.8 (7) |
| issn | 2158-107X 2156-5570 |
| language | eng |
| recordid | cdi_proquest_journals_2656439828 |
| source | Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals |
| subjects | Algorithms Arithmetic coding Binary codes Coders Computer science Digital signal processors Hardware Power consumption Software |
| title | Low-Power Hardware Design of Binary Arithmetic Encoder in H.264 |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T13%3A51%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Low-Power%20Hardware%20Design%20of%20Binary%20Arithmetic%20Encoder%20in%20H.264&rft.jtitle=International%20journal%20of%20advanced%20computer%20science%20&%20applications&rft.au=Hamida,%20Ben&rft.date=2017-01-01&rft.volume=8&rft.issue=7&rft.issn=2158-107X&rft.eissn=2156-5570&rft_id=info:doi/10.14569/IJACSA.2017.080756&rft_dat=%3Cproquest_cross%3E2656439828%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2656439828&rft_id=info:pmid/&rfr_iscdi=true |