Low power, high speed approximate multiplier for error resilient applications

This paper proposes novel constant carry-based approximate compressors for partial product reduction in the binary multiplier. The constant carry compressors have only Sum as output and the output carry bits are either constant 0 or 1 and hence no requirement of logic computation. This will evidentl...

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Veröffentlicht in:	Integration (Amsterdam) 2022-05, Vol.84, p.37-46
Hauptverfasser:	S., Skandha Deepsita, Sk, Noor Mahammad
Format:	Artikel
Sprache:	eng
Schlagworte:	Acceptable noise levels Approximate circuits Approximate multipliers Arithmetic circuits Binary system Chains Compressors Delay Discrete Cosine Transform Edge detection Energy efficient Mathematical functions Multipliers Reduction
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