A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network

Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the v...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Circuits, systems, and signal processing systems, and signal processing, 2022-04, Vol.41 (4), p.2308-2321
Hauptverfasser: Mayakkannan, A. V., Rajendran, Selvakumar, Kannan, Srihari, Chakrapani, Arvind, Shanmuganathan, V. K.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 2321
container_issue 4
container_start_page 2308
container_title Circuits, systems, and signal processing
container_volume 41
creator Mayakkannan, A. V.
Rajendran, Selvakumar
Kannan, Srihari
Chakrapani, Arvind
Shanmuganathan, V. K.
description Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204  μ m 2 (12  μ m  ×  17  μ m).
doi_str_mv 10.1007/s00034-021-01864-w
format Article
fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_journals_2634670957</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2634670957</sourcerecordid><originalsourceid>FETCH-LOGICAL-c270t-ccd873549d8c020381b38096534adfc7a1cb3977b3d5b0733dfe746fb72612f93</originalsourceid><addsrcrecordid>eNp9kM9LwzAYhoMoOKf_gKeA5-iXpG3S45jVDYYKc-At9EfSZda2Ju3G_nurFbx5-t7D-7wfPAhdU7ilAOLOAwAPCDBKgMooIIcTNKEhpySUQp6iCTAhCUj6do4uvN8B0DiI2QSVM7xuK9uRZd32Hb53dq8dSeo0q3SBF7bcknWrh5jWBU5q7cojSYyxudV1h1d6ryu83lrTaYc33tYlXhwzZwv80lcV2bT4SXeHxr1fojOTVl5f_d4p2jwkr_MFWT0_LuezFcmZgI7keSEFD4O4kDkw4JJmXEIchTxIC5OLlOYZj4XIeBFmIDgvjBZBZDLBIspMzKfoZtxtXfPZa9-pXdO7enipWMSDSEAciqHFxlbuGu-dNqp19iN1R0VBfQtVo1A1CFU_QtVhgPgI-aFcl9r9Tf9DfQH4YXhY</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2634670957</pqid></control><display><type>article</type><title>A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network</title><source>SpringerLink Journals - AutoHoldings</source><creator>Mayakkannan, A. V. ; Rajendran, Selvakumar ; Kannan, Srihari ; Chakrapani, Arvind ; Shanmuganathan, V. K.</creator><creatorcontrib>Mayakkannan, A. V. ; Rajendran, Selvakumar ; Kannan, Srihari ; Chakrapani, Arvind ; Shanmuganathan, V. K.</creatorcontrib><description>Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204  μ m 2 (12  μ m  ×  17  μ m).</description><identifier>ISSN: 0278-081X</identifier><identifier>EISSN: 1531-5878</identifier><identifier>DOI: 10.1007/s00034-021-01864-w</identifier><language>eng</language><publisher>New York: Springer US</publisher><subject>Circuits and Systems ; Current mirrors ; Electrical Engineering ; Electronics and Microelectronics ; Energy consumption ; Energy efficiency ; Engineering ; Instrumentation ; Integrated circuits ; Power consumption ; Short Paper ; Signal,Image and Speech Processing ; Simulation ; Transistors ; Voltage drop</subject><ispartof>Circuits, systems, and signal processing, 2022-04, Vol.41 (4), p.2308-2321</ispartof><rights>The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021</rights><rights>The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2021.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c270t-ccd873549d8c020381b38096534adfc7a1cb3977b3d5b0733dfe746fb72612f93</cites><orcidid>0000-0002-1740-3944 ; 0000-0001-7867-5575 ; 0000-0002-8210-1491 ; 0000-0002-5456-7438 ; 0000-0002-2829-830X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s00034-021-01864-w$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s00034-021-01864-w$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,41488,42557,51319</link.rule.ids></links><search><creatorcontrib>Mayakkannan, A. V.</creatorcontrib><creatorcontrib>Rajendran, Selvakumar</creatorcontrib><creatorcontrib>Kannan, Srihari</creatorcontrib><creatorcontrib>Chakrapani, Arvind</creatorcontrib><creatorcontrib>Shanmuganathan, V. K.</creatorcontrib><title>A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network</title><title>Circuits, systems, and signal processing</title><addtitle>Circuits Syst Signal Process</addtitle><description>Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204  μ m 2 (12  μ m  ×  17  μ m).</description><subject>Circuits and Systems</subject><subject>Current mirrors</subject><subject>Electrical Engineering</subject><subject>Electronics and Microelectronics</subject><subject>Energy consumption</subject><subject>Energy efficiency</subject><subject>Engineering</subject><subject>Instrumentation</subject><subject>Integrated circuits</subject><subject>Power consumption</subject><subject>Short Paper</subject><subject>Signal,Image and Speech Processing</subject><subject>Simulation</subject><subject>Transistors</subject><subject>Voltage drop</subject><issn>0278-081X</issn><issn>1531-5878</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp9kM9LwzAYhoMoOKf_gKeA5-iXpG3S45jVDYYKc-At9EfSZda2Ju3G_nurFbx5-t7D-7wfPAhdU7ilAOLOAwAPCDBKgMooIIcTNKEhpySUQp6iCTAhCUj6do4uvN8B0DiI2QSVM7xuK9uRZd32Hb53dq8dSeo0q3SBF7bcknWrh5jWBU5q7cojSYyxudV1h1d6ryu83lrTaYc33tYlXhwzZwv80lcV2bT4SXeHxr1fojOTVl5f_d4p2jwkr_MFWT0_LuezFcmZgI7keSEFD4O4kDkw4JJmXEIchTxIC5OLlOYZj4XIeBFmIDgvjBZBZDLBIspMzKfoZtxtXfPZa9-pXdO7enipWMSDSEAciqHFxlbuGu-dNqp19iN1R0VBfQtVo1A1CFU_QtVhgPgI-aFcl9r9Tf9DfQH4YXhY</recordid><startdate>20220401</startdate><enddate>20220401</enddate><creator>Mayakkannan, A. V.</creator><creator>Rajendran, Selvakumar</creator><creator>Kannan, Srihari</creator><creator>Chakrapani, Arvind</creator><creator>Shanmuganathan, V. K.</creator><general>Springer US</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7SC</scope><scope>7SP</scope><scope>7XB</scope><scope>88I</scope><scope>8AL</scope><scope>8AO</scope><scope>8FD</scope><scope>8FE</scope><scope>8FG</scope><scope>8FK</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>L6V</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>M0N</scope><scope>M2P</scope><scope>M7S</scope><scope>P5Z</scope><scope>P62</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope><scope>Q9U</scope><scope>S0W</scope><orcidid>https://orcid.org/0000-0002-1740-3944</orcidid><orcidid>https://orcid.org/0000-0001-7867-5575</orcidid><orcidid>https://orcid.org/0000-0002-8210-1491</orcidid><orcidid>https://orcid.org/0000-0002-5456-7438</orcidid><orcidid>https://orcid.org/0000-0002-2829-830X</orcidid></search><sort><creationdate>20220401</creationdate><title>A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network</title><author>Mayakkannan, A. V. ; Rajendran, Selvakumar ; Kannan, Srihari ; Chakrapani, Arvind ; Shanmuganathan, V. K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c270t-ccd873549d8c020381b38096534adfc7a1cb3977b3d5b0733dfe746fb72612f93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Circuits and Systems</topic><topic>Current mirrors</topic><topic>Electrical Engineering</topic><topic>Electronics and Microelectronics</topic><topic>Energy consumption</topic><topic>Energy efficiency</topic><topic>Engineering</topic><topic>Instrumentation</topic><topic>Integrated circuits</topic><topic>Power consumption</topic><topic>Short Paper</topic><topic>Signal,Image and Speech Processing</topic><topic>Simulation</topic><topic>Transistors</topic><topic>Voltage drop</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mayakkannan, A. V.</creatorcontrib><creatorcontrib>Rajendran, Selvakumar</creatorcontrib><creatorcontrib>Kannan, Srihari</creatorcontrib><creatorcontrib>Chakrapani, Arvind</creatorcontrib><creatorcontrib>Shanmuganathan, V. K.</creatorcontrib><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>Science Database (Alumni Edition)</collection><collection>Computing Database (Alumni Edition)</collection><collection>ProQuest Pharma Collection</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>Materials Science &amp; Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies &amp; Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>ProQuest Engineering Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Computing Database</collection><collection>Science Database</collection><collection>Engineering Database</collection><collection>Advanced Technologies &amp; Aerospace Database</collection><collection>ProQuest Advanced Technologies &amp; Aerospace Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><collection>ProQuest Central Basic</collection><collection>DELNET Engineering &amp; Technology Collection</collection><jtitle>Circuits, systems, and signal processing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Mayakkannan, A. V.</au><au>Rajendran, Selvakumar</au><au>Kannan, Srihari</au><au>Chakrapani, Arvind</au><au>Shanmuganathan, V. K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network</atitle><jtitle>Circuits, systems, and signal processing</jtitle><stitle>Circuits Syst Signal Process</stitle><date>2022-04-01</date><risdate>2022</risdate><volume>41</volume><issue>4</issue><spage>2308</spage><epage>2321</epage><pages>2308-2321</pages><issn>0278-081X</issn><eissn>1531-5878</eissn><abstract>Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204  μ m 2 (12  μ m  ×  17  μ m).</abstract><cop>New York</cop><pub>Springer US</pub><doi>10.1007/s00034-021-01864-w</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0002-1740-3944</orcidid><orcidid>https://orcid.org/0000-0001-7867-5575</orcidid><orcidid>https://orcid.org/0000-0002-8210-1491</orcidid><orcidid>https://orcid.org/0000-0002-5456-7438</orcidid><orcidid>https://orcid.org/0000-0002-2829-830X</orcidid></addata></record>
fulltext fulltext
identifier ISSN: 0278-081X
ispartof Circuits, systems, and signal processing, 2022-04, Vol.41 (4), p.2308-2321
issn 0278-081X
1531-5878
language eng
recordid cdi_proquest_journals_2634670957
source SpringerLink Journals - AutoHoldings
subjects Circuits and Systems
Current mirrors
Electrical Engineering
Electronics and Microelectronics
Energy consumption
Energy efficiency
Engineering
Instrumentation
Integrated circuits
Power consumption
Short Paper
Signal,Image and Speech Processing
Simulation
Transistors
Voltage drop
title A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T15%3A07%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20Split-Input%20Driver-Enabled%20High-Speed%20and%20Energy-Efficient%20Level%20Shifter%20Using%20Hybrid%20Pull-Up%20Network&rft.jtitle=Circuits,%20systems,%20and%20signal%20processing&rft.au=Mayakkannan,%20A.%20V.&rft.date=2022-04-01&rft.volume=41&rft.issue=4&rft.spage=2308&rft.epage=2321&rft.pages=2308-2321&rft.issn=0278-081X&rft.eissn=1531-5878&rft_id=info:doi/10.1007/s00034-021-01864-w&rft_dat=%3Cproquest_cross%3E2634670957%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2634670957&rft_id=info:pmid/&rfr_iscdi=true