A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network
Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the v...
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Veröffentlicht in: | Circuits, systems, and signal processing systems, and signal processing, 2022-04, Vol.41 (4), p.2308-2321 |
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creator | Mayakkannan, A. V. Rajendran, Selvakumar Kannan, Srihari Chakrapani, Arvind Shanmuganathan, V. K. |
description | Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204
μ
m
2
(12
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17
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m). |
doi_str_mv | 10.1007/s00034-021-01864-w |
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V.</au><au>Rajendran, Selvakumar</au><au>Kannan, Srihari</au><au>Chakrapani, Arvind</au><au>Shanmuganathan, V. K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network</atitle><jtitle>Circuits, systems, and signal processing</jtitle><stitle>Circuits Syst Signal Process</stitle><date>2022-04-01</date><risdate>2022</risdate><volume>41</volume><issue>4</issue><spage>2308</spage><epage>2321</epage><pages>2308-2321</pages><issn>0278-081X</issn><eissn>1531-5878</eissn><abstract>Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204
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subjects | Circuits and Systems Current mirrors Electrical Engineering Electronics and Microelectronics Energy consumption Energy efficiency Engineering Instrumentation Integrated circuits Power consumption Short Paper Signal,Image and Speech Processing Simulation Transistors Voltage drop |
title | A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network |
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