Efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring for parallelization in high‐level synthesis

Summary This paper describes a fast and efficient hardware‐accelerated pseudoinverse computation through algorithm restructuring and leveraging FPGA synthesis directives for parallelism prior to high‐level synthesis (HLS). The algorithm, which is composed of modified Gram–Schmidt QR decomposition (M...

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Veröffentlicht in:	International journal of circuit theory and applications 2022-02, Vol.50 (2), p.394-416
Hauptverfasser:	Tan, Chong Yeam, Ooi, Chia Yee, Choo, Hau Sim, Ismail, Nordinah
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Computational efficiency Field programmable gate arrays Gram–Schmidt QR decomposition Hardware high‐level synthesis loop optimization Matrices (mathematics) Modules Multiplication Parallel processing pseudoinverse Reduction Synthesis
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