Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress
Multilevel inverters with a high device count, low boosting and DC voltage imbalance are all common problems exists in the traditional topologies. In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower tota...
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description | Multilevel inverters with a high device count, low boosting and DC voltage imbalance are all common problems exists in the traditional topologies. In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented. The multiple input sources of the proposed inverter make it suited for the use in renewable energy generating systems which have a variety of DC sources. The stress distribution among the switches is investigated that reduces the use of high rated devices with which overall cost of the inverter gets reduced. The topology can be extended by adding the circuits in series for higher levels. The performance of the inverter is calculated considering a variety of critical parameters such as TSV, cost function (CF), power loss, and efficiency calculations. The MLI is tested under dynamic load conditions with sudden load disturbances with a range of combinational loads and it has been determined to be stable throughout its operation. A detailed comparison is made based on stress across the switches, stress distribution, switches count, DC sources count, gate driver circuits, component count factor, TSV, CF, and other existing topologies using graphical representations and shown to be cost-effective and superior in all aspects. The total harmonic distortion (THD) derived from simulation and experiment complies with IEEE standards. The proposed framework has been developed in MATLAB/Simulink and tested in a laboratory environment with hardware. |
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In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented. The multiple input sources of the proposed inverter make it suited for the use in renewable energy generating systems which have a variety of DC sources. The stress distribution among the switches is investigated that reduces the use of high rated devices with which overall cost of the inverter gets reduced. The topology can be extended by adding the circuits in series for higher levels. The performance of the inverter is calculated considering a variety of critical parameters such as TSV, cost function (CF), power loss, and efficiency calculations. The MLI is tested under dynamic load conditions with sudden load disturbances with a range of combinational loads and it has been determined to be stable throughout its operation. A detailed comparison is made based on stress across the switches, stress distribution, switches count, DC sources count, gate driver circuits, component count factor, TSV, CF, and other existing topologies using graphical representations and shown to be cost-effective and superior in all aspects. The total harmonic distortion (THD) derived from simulation and experiment complies with IEEE standards. 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(IEEE) 2022</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c408t-976150d825d25fbb56deb63ef12dd3b6b9bdfe66192b76eb458579fd9448bb103</citedby><cites>FETCH-LOGICAL-c408t-976150d825d25fbb56deb63ef12dd3b6b9bdfe66192b76eb458579fd9448bb103</cites><orcidid>0000-0003-0054-0149 ; 0000-0002-9491-5476</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9668936$$EHTML$$P50$$Gieee$$Hfree_for_read</linktohtml><link.rule.ids>314,776,780,860,2096,4010,27610,27900,27901,27902,54908</link.rule.ids></links><search><creatorcontrib>Khasim, Shaik Reddi</creatorcontrib><creatorcontrib>Dhanamjayulu, C.</creatorcontrib><title>Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress</title><title>IEEE access</title><addtitle>Access</addtitle><description>Multilevel inverters with a high device count, low boosting and DC voltage imbalance are all common problems exists in the traditional topologies. In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented. The multiple input sources of the proposed inverter make it suited for the use in renewable energy generating systems which have a variety of DC sources. The stress distribution among the switches is investigated that reduces the use of high rated devices with which overall cost of the inverter gets reduced. The topology can be extended by adding the circuits in series for higher levels. The performance of the inverter is calculated considering a variety of critical parameters such as TSV, cost function (CF), power loss, and efficiency calculations. The MLI is tested under dynamic load conditions with sudden load disturbances with a range of combinational loads and it has been determined to be stable throughout its operation. A detailed comparison is made based on stress across the switches, stress distribution, switches count, DC sources count, gate driver circuits, component count factor, TSV, CF, and other existing topologies using graphical representations and shown to be cost-effective and superior in all aspects. The total harmonic distortion (THD) derived from simulation and experiment complies with IEEE standards. The proposed framework has been developed in MATLAB/Simulink and tested in a laboratory environment with hardware.</description><subject>Asymmetry</subject><subject>Cost function</subject><subject>cost function (CF)</subject><subject>Driver circuits</subject><subject>Dynamic loads</subject><subject>Gates (circuits)</subject><subject>Graphical representations</subject><subject>Harmonic distortion</subject><subject>Inverters</subject><subject>Low voltage</subject><subject>Mathematical analysis</subject><subject>Mathematical models</subject><subject>maximum blocking voltage (MBV)</subject><subject>Multilevel</subject><subject>Multilevel inverter</subject><subject>Multilevel inverters</subject><subject>normalised voltage stress (NVS)</subject><subject>Stress</subject><subject>Stress distribution</subject><subject>Switches</subject><subject>Through-silicon vias</subject><subject>Topology</subject><subject>total harmonic distortion (THD)</subject><subject>total standing voltage (TSV)</subject><subject>Voltage</subject><issn>2169-3536</issn><issn>2169-3536</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>ESBDL</sourceid><sourceid>RIE</sourceid><sourceid>DOA</sourceid><recordid>eNpNUU1rGzEUXEoLDUl-QS6Cnu3qe1dHs01bg0Oh7sdRSKsnV0a7ciU5If--m2wIfZf3GGbmDUzT3BC8JgSrj5u-v93v1xRTumaEYyb4m-aCEqlWTDD59r_7fXNdyhHP082QaC-a-AlKOEzITA5tx1OEEaZqakgTSh5tyuM4Qs1hMBHdnWMNEe4hou10D7lCRr9D_YO-gzsP4FCfxlOaZn15ttulB_QrxWoOgPY1QylXzTtvYoHrl33Z_Px8-6P_utp9-7LtN7vVwHFXV6qVRGDXUeGo8NYK6cBKBp5Q55iVVlnnQUqiqG0lWC460SrvFOedtQSzy2a7-LpkjvqUw2jyo04m6Gcg5YM2uYYhgvaOYTUobpQhXDhsfDeAl0w43jrS8dnrw-J1yunvGUrVx3TO0xxf0zkBJm3LycxiC2vIqZQM_vUrwfqpJb20pJ9a0i8tzaqbRRUA4FWhpOwUk-wfmV-O6g</recordid><startdate>2022</startdate><enddate>2022</enddate><creator>Khasim, Shaik Reddi</creator><creator>Dhanamjayulu, C.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>ESBDL</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7SR</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>DOA</scope><orcidid>https://orcid.org/0000-0003-0054-0149</orcidid><orcidid>https://orcid.org/0000-0002-9491-5476</orcidid></search><sort><creationdate>2022</creationdate><title>Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress</title><author>Khasim, Shaik Reddi ; Dhanamjayulu, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c408t-976150d825d25fbb56deb63ef12dd3b6b9bdfe66192b76eb458579fd9448bb103</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Asymmetry</topic><topic>Cost function</topic><topic>cost function (CF)</topic><topic>Driver circuits</topic><topic>Dynamic loads</topic><topic>Gates (circuits)</topic><topic>Graphical representations</topic><topic>Harmonic distortion</topic><topic>Inverters</topic><topic>Low voltage</topic><topic>Mathematical analysis</topic><topic>Mathematical models</topic><topic>maximum blocking voltage (MBV)</topic><topic>Multilevel</topic><topic>Multilevel inverter</topic><topic>Multilevel inverters</topic><topic>normalised voltage stress (NVS)</topic><topic>Stress</topic><topic>Stress distribution</topic><topic>Switches</topic><topic>Through-silicon vias</topic><topic>Topology</topic><topic>total harmonic distortion (THD)</topic><topic>total standing voltage (TSV)</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Khasim, Shaik Reddi</creatorcontrib><creatorcontrib>Dhanamjayulu, C.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE Open Access Journals</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>DOAJ Directory of Open Access Journals</collection><jtitle>IEEE access</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Khasim, Shaik Reddi</au><au>Dhanamjayulu, C.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress</atitle><jtitle>IEEE access</jtitle><stitle>Access</stitle><date>2022</date><risdate>2022</risdate><volume>10</volume><spage>3495</spage><epage>3511</epage><pages>3495-3511</pages><issn>2169-3536</issn><eissn>2169-3536</eissn><coden>IAECCG</coden><abstract>Multilevel inverters with a high device count, low boosting and DC voltage imbalance are all common problems exists in the traditional topologies. In this article, a new single-phase asymmetrical multilevel inverter (MLI) that can generate 33 levels at the output with fewer components and lower total standing voltage (TSV) at the switches is presented. The multiple input sources of the proposed inverter make it suited for the use in renewable energy generating systems which have a variety of DC sources. The stress distribution among the switches is investigated that reduces the use of high rated devices with which overall cost of the inverter gets reduced. The topology can be extended by adding the circuits in series for higher levels. The performance of the inverter is calculated considering a variety of critical parameters such as TSV, cost function (CF), power loss, and efficiency calculations. The MLI is tested under dynamic load conditions with sudden load disturbances with a range of combinational loads and it has been determined to be stable throughout its operation. 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subjects | Asymmetry Cost function cost function (CF) Driver circuits Dynamic loads Gates (circuits) Graphical representations Harmonic distortion Inverters Low voltage Mathematical analysis Mathematical models maximum blocking voltage (MBV) Multilevel Multilevel inverter Multilevel inverters normalised voltage stress (NVS) Stress Stress distribution Switches Through-silicon vias Topology total harmonic distortion (THD) total standing voltage (TSV) Voltage |
title | Design and Implementation of Asymmetrical Multilevel Inverter With Reduced Components and Low Voltage Stress |
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