Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters

This paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained from extracted layout view with parasitics. The synthe...

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Veröffentlicht in:	Analog integrated circuits and signal processing 2021-12, Vol.109 (3), p.647-656
Hauptverfasser:	Castro, Mateus B., Souza, Raphael R. N., Junior, Agord M. P., Lima, Eduardo R., Manera, Leandro T.
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog to digital conversion Analog to digital converters Circuits and Systems CMOS Electrical Engineering Engineering Oversampling Phase locked loops Reconfiguration Signal to noise ratio Signal,Image and Speech Processing Synthesis Vibration
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