Selective branch prediction schemes based on FPGA MIPS processor for educational purposes

Processor performance is measured by amount of ILP (Instruction Level Parallelism) represented by its design. this parallelism is limited by the execution of conditional branch instructions which may break the flow of the program execution. To overcome this problem, several ways were suggested in or...

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Veröffentlicht in:	IOP conference series. Materials Science and Engineering 2019-05, Vol.518 (4), p.42008
Hauptverfasser:	Mahmood, H S, Omran, S S
Format:	Artikel
Sprache:	eng
Schlagworte:	Field programmable gate arrays Hardware description languages Integrated software Microprocessors VHSIC (circuits)
Online-Zugang:	Volltext
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