A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration
Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with d...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2021-08, Vol.56 (8), p.2525-2538 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 56 |
| creator | Choo, Min-Seong Kim, Sungwoo Ko, Han-Gon Cho, Sung-Yong Park, Kwanseo Lee, Jinhyung Shin, Soyeong Chi, Hankyu Jeong, Deog-Kyoon |
| description | Although an injection-locked oscillator (ILO) can offer excellent jitter performance on average, its intense phase modification at a given injection rate inevitably degrades spur performance, unless injection timing is carefully controlled. This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis on the dynamics of the digital injection-locked clock multiplier (ILCM) is provided. Adjusting frequency error between the free-running oscillator and the injection signal is crucial to obtain better spur performance. However, the timing offset caused by the device mismatches hinders it from being correctly compensated. Therefore, we investigate the effect of timing offset (or mismatch) between the replica cells and BBPD and then propose the time-division dual calibration (TDDC) to reduce the discrepancies. In addition, three-stage replica cells are chosen to achieve a robust operation in the phase generating aspect. By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed. |
| doi_str_mv | 10.1109/JSSC.2021.3062554 |
| format | Article |
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This work investigates a behavioral model of the ILO with digital control of a bang-bang phase detector (BBPD) on a discrete-time domain, a quantitative analysis on the dynamics of the digital injection-locked clock multiplier (ILCM) is provided. Adjusting frequency error between the free-running oscillator and the injection signal is crucial to obtain better spur performance. However, the timing offset caused by the device mismatches hinders it from being correctly compensated. Therefore, we investigate the effect of timing offset (or mismatch) between the replica cells and BBPD and then propose the time-division dual calibration (TDDC) to reduce the discrepancies. In addition, three-stage replica cells are chosen to achieve a robust operation in the phase generating aspect. By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2021.3062554</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>a bang-bang phase detector (BBPD) ; All-digital ; Calibration ; Clocks ; Delays ; Detectors ; Division ; frequency calibration loop (FCL) ; injection-locked clock multiplication (ILCM) ; injection-locked oscillator (ILO) ; Jitter ; Locking ; path-mismatch calibration loop (PCL) ; Performance degradation ; Phase detectors ; phase domain response (PDR) ; Phase locked loops ; Robustness ; Time domain analysis ; time-division dual calibration (TDDC) ; Vibration</subject><ispartof>IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2525-2538</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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By removing the residual phase offset using multiple delay cells, the optimum locking point is guaranteed.</description><subject>a bang-bang phase detector (BBPD)</subject><subject>All-digital</subject><subject>Calibration</subject><subject>Clocks</subject><subject>Delays</subject><subject>Detectors</subject><subject>Division</subject><subject>frequency calibration loop (FCL)</subject><subject>injection-locked clock multiplication (ILCM)</subject><subject>injection-locked oscillator (ILO)</subject><subject>Jitter</subject><subject>Locking</subject><subject>path-mismatch calibration loop (PCL)</subject><subject>Performance degradation</subject><subject>Phase detectors</subject><subject>phase domain response (PDR)</subject><subject>Phase locked loops</subject><subject>Robustness</subject><subject>Time domain analysis</subject><subject>time-division dual calibration (TDDC)</subject><subject>Vibration</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kFtLwzAUx4MoOKcfQHwJ-NyZW5v0cXRemUx0Tt9KliYzW7bOpBX8Bn5s0018OYfD-V_gB8A5RgOMUX718PJSDAgieEBRRtKUHYAeTlORYE7fD0EPISySnCB0DE5CWMaTMYF74GcIn2ZTOJPeysbWm-S5nrehgUPnkpFd2EY6eL9ZarV7jmu10hUsXNzwsXWN3TqrPXyzzQd81tIlU7vWcGJM0A2ceqlWdrOAr6Gb3StmftkQo-CojcmFdHbud8Wn4MhIF_TZ3-6D15vraXGXjCe398VwnCiS0yahqBI6YxXFxnCDFMlkjhSnsuIsyxjTfK4MFyhjhIg5V4LqlEmkcmGQqbSkfXC5z936-rPVoSmXdes3sbKM2FJOUp7xqMJ7lfJ1CF6bcuvtWvrvEqOyA152wMsOePkHPHou9h6rtf7X51RkBGP6C0eNfRE</recordid><startdate>20210801</startdate><enddate>20210801</enddate><creator>Choo, Min-Seong</creator><creator>Kim, Sungwoo</creator><creator>Ko, Han-Gon</creator><creator>Cho, Sung-Yong</creator><creator>Park, Kwanseo</creator><creator>Lee, Jinhyung</creator><creator>Shin, Soyeong</creator><creator>Chi, Hankyu</creator><creator>Jeong, Deog-Kyoon</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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| ispartof | IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2525-2538 |
| issn | 0018-9200 1558-173X |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | a bang-bang phase detector (BBPD) All-digital Calibration Clocks Delays Detectors Division frequency calibration loop (FCL) injection-locked clock multiplication (ILCM) injection-locked oscillator (ILO) Jitter Locking path-mismatch calibration loop (PCL) Performance degradation Phase detectors phase domain response (PDR) Phase locked loops Robustness Time domain analysis time-division dual calibration (TDDC) Vibration |
| title | A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration |
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