Simple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method With Hysteresis Neutral-Point Error Band
Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions f...
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Veröffentlicht in: | IEEE transactions on power electronics 2021-11, Vol.36 (11), p.12490-12503 |
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description | Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results. |
doi_str_mv | 10.1109/TPEL.2021.3074957 |
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However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results.</description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2021.3074957</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Balancing ; Capacitance ; Capacitance-voltage characteristics ; Capacitors ; Clamps ; Control methods ; Discontinuous pulsewidth modulation (DPWM) ; Electric potential ; Error analysis ; Harmonic distortion ; Hysteresis ; hysteresis neutral-point (NP) error band ; Inverters ; NP voltage balancing ; Power semiconductor devices ; Pulse duration ; Switches ; three-level NP clamped inverter (3L-NPC) ; Voltage ; Voltage control ; Waveforms</subject><ispartof>IEEE transactions on power electronics, 2021-11, Vol.36 (11), p.12490-12503</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c223t-da3aff4a420ecc262973f9ae579f4f14dce9d6a4f9756f757bc77164532aba2f3</citedby><cites>FETCH-LOGICAL-c223t-da3aff4a420ecc262973f9ae579f4f14dce9d6a4f9756f757bc77164532aba2f3</cites><orcidid>0000-0002-2670-3789 ; 0000-0002-2125-9500</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9411695$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9411695$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Alsofyani, Ibrahim Mohd</creatorcontrib><creatorcontrib>Lee, Kyo-Beum</creatorcontrib><title>Simple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method With Hysteresis Neutral-Point Error Band</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description>Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results.</description><subject>Balancing</subject><subject>Capacitance</subject><subject>Capacitance-voltage characteristics</subject><subject>Capacitors</subject><subject>Clamps</subject><subject>Control methods</subject><subject>Discontinuous pulsewidth modulation (DPWM)</subject><subject>Electric potential</subject><subject>Error analysis</subject><subject>Harmonic distortion</subject><subject>Hysteresis</subject><subject>hysteresis neutral-point (NP) error band</subject><subject>Inverters</subject><subject>NP voltage balancing</subject><subject>Power semiconductor devices</subject><subject>Pulse duration</subject><subject>Switches</subject><subject>three-level NP clamped inverter (3L-NPC)</subject><subject>Voltage</subject><subject>Voltage control</subject><subject>Waveforms</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kd1KAzEQRoMoWH8eQLwJeL01ySab5lJr1UKrBau9XNLsxEbWTU2yhT6Br-2WFq8GhvN9A2cQuqKkTylRt_PZaNJnhNF-TiRXQh6hHlWcZoQSeYx6ZDAQ2UCp_BSdxfhFCOWC0B76fXPf6xrwUK-1cckH_OHrpD8B3-taN8Y1n9h22_kqAGQT2ECNX2ZDPG42EBIE_B53yIOLxjfJNa1vI54tpngKaeUrvHBphZ-3sUMhuohfoE1B19nMuybhUQhd971uqgt0YnUd4fIwz9H742g-fM4mr0_j4d0kM4zlKat0rq3lmjMCxrCCKZlbpUFIZbmlvDKgqkJzq6QorBRyaaSkBRc500vNbH6Obva96-B_Woip_PJtaLqTJRNCSMaLougouqdM8DEGsOU6uG8dtiUl5c53ufNd7nyXB99d5nqfcQDwz3cvoIUS-R-qRn2S</recordid><startdate>20211101</startdate><enddate>20211101</enddate><creator>Alsofyani, Ibrahim Mohd</creator><creator>Lee, Kyo-Beum</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-2670-3789</orcidid><orcidid>https://orcid.org/0000-0002-2125-9500</orcidid></search><sort><creationdate>20211101</creationdate><title>Simple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method With Hysteresis Neutral-Point Error Band</title><author>Alsofyani, Ibrahim Mohd ; Lee, Kyo-Beum</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c223t-da3aff4a420ecc262973f9ae579f4f14dce9d6a4f9756f757bc77164532aba2f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>Balancing</topic><topic>Capacitance</topic><topic>Capacitance-voltage characteristics</topic><topic>Capacitors</topic><topic>Clamps</topic><topic>Control methods</topic><topic>Discontinuous pulsewidth modulation (DPWM)</topic><topic>Electric potential</topic><topic>Error analysis</topic><topic>Harmonic distortion</topic><topic>Hysteresis</topic><topic>hysteresis neutral-point (NP) error band</topic><topic>Inverters</topic><topic>NP voltage balancing</topic><topic>Power semiconductor devices</topic><topic>Pulse duration</topic><topic>Switches</topic><topic>three-level NP clamped inverter (3L-NPC)</topic><topic>Voltage</topic><topic>Voltage control</topic><topic>Waveforms</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Alsofyani, Ibrahim Mohd</creatorcontrib><creatorcontrib>Lee, Kyo-Beum</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Alsofyani, Ibrahim Mohd</au><au>Lee, Kyo-Beum</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Simple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method With Hysteresis Neutral-Point Error Band</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2021-11-01</date><risdate>2021</risdate><volume>36</volume><issue>11</issue><spage>12490</spage><epage>12503</epage><pages>12490-12503</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract>Three-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2021.3074957</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0002-2670-3789</orcidid><orcidid>https://orcid.org/0000-0002-2125-9500</orcidid></addata></record> |
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subjects | Balancing Capacitance Capacitance-voltage characteristics Capacitors Clamps Control methods Discontinuous pulsewidth modulation (DPWM) Electric potential Error analysis Harmonic distortion Hysteresis hysteresis neutral-point (NP) error band Inverters NP voltage balancing Power semiconductor devices Pulse duration Switches three-level NP clamped inverter (3L-NPC) Voltage Voltage control Waveforms |
title | Simple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method With Hysteresis Neutral-Point Error Band |
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