A High-Speed PWM-Modulated Transceiver Network for Closed-Loop Channel Topology
This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of prop...
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| Veröffentlicht in: | IEICE Transactions on Electronics 2021/07/01, Vol.E104.C(7), pp.350-354 |
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| container_title | IEICE Transactions on Electronics |
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| creator | LEE, Kyongsu SIM, Jae-Yoon |
| description | This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability. |
| doi_str_mv | 10.1587/transele.2020CDS0001 |
| format | Article |
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To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. 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Electron.</addtitle><description>This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. 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| subjects | automotive communication Channels clock and data recovery Clock recovery CMOS Control equipment Data recovery Electronic control high-speed transceiver interface circuits Pulse duration modulation pulse-width modulation Topology Transceivers |
| title | A High-Speed PWM-Modulated Transceiver Network for Closed-Loop Channel Topology |
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