Defect and Fault Modeling Framework for STT-MRAM Testing

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This article presents a systematic device-aware defect and fault modeling...

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Veröffentlicht in:	IEEE transactions on emerging topics in computing 2021-04, Vol.9 (2), p.707-723
Hauptverfasser:	Wu, Lizhou, Rao, Siddharth, Taouil, Mottaqiallah, Medeiros, Guilherme Cardoso, Fieback, Moritz, Marinissen, Erik Jan, Kar, Gouri Sankar, Hamdioui, Said
Format:	Artikel
Sprache:	eng
Schlagworte:	Commercialization Defects Electronic devices fault models Foundries Magnetic anisotropy Magnetic properties Magnetic tunneling Magnetization Manufacturing defects Mass production Mathematical models Modelling Multiprotocol label switching Parameters Pinhole defects Resistors Saturation magnetization STT-MRAM Switches test development Tunnel junctions
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