Modulating the Transport Properties of Metal Oxide Nanofibers Transistors by Controlling the Grain Size
Although SnO 2 nanofibers (NFs) are one of the good candidates as active materials for next-generation consumable electronics, these NFs based devices still suffer from insufficient on-off current ratios, large and negative threshold voltages ( \text{V}_{\mathbf {TH}} ), leading to high energy consu...
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| Veröffentlicht in: | IEEE electron device letters 2021-06, Vol.42 (6), p.855-858 |
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| creator | Zu, Hongliang Chang, Yu Li, Hao He, Junyu Li, Jiayi Zhu, Xinxu Zhang, Jun Wang, Fengyun |
| description | Although SnO 2 nanofibers (NFs) are one of the good candidates as active materials for next-generation consumable electronics, these NFs based devices still suffer from insufficient on-off current ratios, large and negative threshold voltages ( \text{V}_{\mathbf {TH}} ), leading to high energy consumption and rather complicated circuit design. Here, SnO 2 NFs field-effect transistors (FET) were fabricated by an electrospinning technique. The device performance can be precisely manipulated by controlling the crystal grain size in the NFs. This is done by simply adjusting the annealing holding time to achieve high-performance enhancement mode. For the optimal annealing holding time of 60 min, the grain size of NFs is about 11 nm, and the devices exhibit the best electrical performance, including a small and positive V TH (≈ 2.2 V), a large switching current ratio (I ON /I OFF ≥ 10 6 ), and proper carrier mobility ( \mu _{\text{FE}} ) (≈ 2.3 cm 2 V −1 s −1 ). Moreover, this approach is universal and can be applied to optimize other metal oxide semiconductors such as ZnO NFs. This simple and facile method indicates that adjusting annealing holding time is a potential way to control the grain size to achieve low voltage operation and enhancement mode 1D metal oxide FETs. |
| doi_str_mv | 10.1109/LED.2021.3073211 |
| format | Article |
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Here, SnO 2 NFs field-effect transistors (FET) were fabricated by an electrospinning technique. The device performance can be precisely manipulated by controlling the crystal grain size in the NFs. This is done by simply adjusting the annealing holding time to achieve high-performance enhancement mode. For the optimal annealing holding time of 60 min, the grain size of NFs is about 11 nm, and the devices exhibit the best electrical performance, including a small and positive V TH (≈ 2.2 V), a large switching current ratio (I ON /I OFF ≥ 10 6 ), and proper carrier mobility (<inline-formula> <tex-math notation="LaTeX">\mu _{\text{FE}} </tex-math></inline-formula>) (≈ 2.3 cm 2 V −1 s −1 ). Moreover, this approach is universal and can be applied to optimize other metal oxide semiconductors such as ZnO NFs. This simple and facile method indicates that adjusting annealing holding time is a potential way to control the grain size to achieve low voltage operation and enhancement mode 1D metal oxide FETs.]]></description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2021.3073211</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>PISCATAWAY: IEEE</publisher><subject>Annealing ; annealing holding time ; Carrier mobility ; Circuit design ; Energy consumption ; Engineering ; Engineering, Electrical & Electronic ; Field effect transistors ; Grain boundaries ; Grain size ; Iron ; Logic gates ; Low voltage ; Metal oxide semiconductors ; Metal oxides ; Nanofibers ; NFs FET ; Optimization ; Performance enhancement ; Performance evaluation ; Science & Technology ; Semiconductor devices ; Technology ; Threshold voltage ; Tin dioxide ; Transistors ; Transport properties ; Zinc oxide</subject><ispartof>IEEE electron device letters, 2021-06, Vol.42 (6), p.855-858</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>true</woscitedreferencessubscribed><woscitedreferencescount>17</woscitedreferencescount><woscitedreferencesoriginalsourcerecordid>wos000652794800019</woscitedreferencesoriginalsourcerecordid><citedby>FETCH-LOGICAL-c291t-ff4ffc359aa6c7257bd3d10735f6f4d0d39a6d42ba01bd8a1df6ae8fcfc519a3</citedby><cites>FETCH-LOGICAL-c291t-ff4ffc359aa6c7257bd3d10735f6f4d0d39a6d42ba01bd8a1df6ae8fcfc519a3</cites><orcidid>0000-0002-5558-423X ; 0000-0003-3607-213X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9404206$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27929,27930,39263,54763</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9404206$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zu, Hongliang</creatorcontrib><creatorcontrib>Chang, Yu</creatorcontrib><creatorcontrib>Li, Hao</creatorcontrib><creatorcontrib>He, Junyu</creatorcontrib><creatorcontrib>Li, Jiayi</creatorcontrib><creatorcontrib>Zhu, Xinxu</creatorcontrib><creatorcontrib>Zhang, Jun</creatorcontrib><creatorcontrib>Wang, Fengyun</creatorcontrib><title>Modulating the Transport Properties of Metal Oxide Nanofibers Transistors by Controlling the Grain Size</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><addtitle>IEEE ELECTR DEVICE L</addtitle><description><![CDATA[Although SnO 2 nanofibers (NFs) are one of the good candidates as active materials for next-generation consumable electronics, these NFs based devices still suffer from insufficient on-off current ratios, large and negative threshold voltages (<inline-formula> <tex-math notation="LaTeX">\text{V}_{\mathbf {TH}} </tex-math></inline-formula>), leading to high energy consumption and rather complicated circuit design. Here, SnO 2 NFs field-effect transistors (FET) were fabricated by an electrospinning technique. The device performance can be precisely manipulated by controlling the crystal grain size in the NFs. This is done by simply adjusting the annealing holding time to achieve high-performance enhancement mode. For the optimal annealing holding time of 60 min, the grain size of NFs is about 11 nm, and the devices exhibit the best electrical performance, including a small and positive V TH (≈ 2.2 V), a large switching current ratio (I ON /I OFF ≥ 10 6 ), and proper carrier mobility (<inline-formula> <tex-math notation="LaTeX">\mu _{\text{FE}} </tex-math></inline-formula>) (≈ 2.3 cm 2 V −1 s −1 ). Moreover, this approach is universal and can be applied to optimize other metal oxide semiconductors such as ZnO NFs. This simple and facile method indicates that adjusting annealing holding time is a potential way to control the grain size to achieve low voltage operation and enhancement mode 1D metal oxide FETs.]]></description><subject>Annealing</subject><subject>annealing holding time</subject><subject>Carrier mobility</subject><subject>Circuit design</subject><subject>Energy consumption</subject><subject>Engineering</subject><subject>Engineering, Electrical & Electronic</subject><subject>Field effect transistors</subject><subject>Grain boundaries</subject><subject>Grain size</subject><subject>Iron</subject><subject>Logic gates</subject><subject>Low voltage</subject><subject>Metal oxide semiconductors</subject><subject>Metal oxides</subject><subject>Nanofibers</subject><subject>NFs FET</subject><subject>Optimization</subject><subject>Performance enhancement</subject><subject>Performance evaluation</subject><subject>Science & Technology</subject><subject>Semiconductor devices</subject><subject>Technology</subject><subject>Threshold voltage</subject><subject>Tin dioxide</subject><subject>Transistors</subject><subject>Transport properties</subject><subject>Zinc oxide</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><sourceid>HGBXW</sourceid><recordid>eNqNkE1v1DAQQCMEEkvhjsTFEkeUZcZfiY8olIK0_ZC698iJ7eIq2IvtVSm_HlcpcO3Jc3hvRn5N8xZhiwjq4-7085YCxS2DjlHEZ80GhehbEJI9bzbQcWwZgnzZvMr5FgA57_imuTmP5rjo4sMNKd8t2Scd8iGmQq5SPNhUvM0kOnJui17I5S9vLLnQITo_2ZRX3OcS6zzdkyGGkuKy_N12lrQP5Nr_tq-bF04v2b55fE-a_ZfT_fC13V2efRs-7dqZKiytc9y5mQmltZw7KrrJMIP1R8JJxw0YprQ0nE4acDK9RuOktr2b3SxQaXbSvF_XHlL8ebS5jLfxmEK9OFLBAFECVZWClZpTzDlZNx6S_6HT_YgwPtQca83xoeb4WLMq_arc2Sm6PHsbZvtPAwApaKd4XydUgy-1aAxDPIZS1Q9PVyv9bqW9tf8pxYFTkOwPaQeTEQ</recordid><startdate>20210601</startdate><enddate>20210601</enddate><creator>Zu, Hongliang</creator><creator>Chang, Yu</creator><creator>Li, Hao</creator><creator>He, Junyu</creator><creator>Li, Jiayi</creator><creator>Zhu, Xinxu</creator><creator>Zhang, Jun</creator><creator>Wang, Fengyun</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Here, SnO 2 NFs field-effect transistors (FET) were fabricated by an electrospinning technique. The device performance can be precisely manipulated by controlling the crystal grain size in the NFs. This is done by simply adjusting the annealing holding time to achieve high-performance enhancement mode. For the optimal annealing holding time of 60 min, the grain size of NFs is about 11 nm, and the devices exhibit the best electrical performance, including a small and positive V TH (≈ 2.2 V), a large switching current ratio (I ON /I OFF ≥ 10 6 ), and proper carrier mobility (<inline-formula> <tex-math notation="LaTeX">\mu _{\text{FE}} </tex-math></inline-formula>) (≈ 2.3 cm 2 V −1 s −1 ). Moreover, this approach is universal and can be applied to optimize other metal oxide semiconductors such as ZnO NFs. This simple and facile method indicates that adjusting annealing holding time is a potential way to control the grain size to achieve low voltage operation and enhancement mode 1D metal oxide FETs.]]></abstract><cop>PISCATAWAY</cop><pub>IEEE</pub><doi>10.1109/LED.2021.3073211</doi><tpages>4</tpages><orcidid>https://orcid.org/0000-0002-5558-423X</orcidid><orcidid>https://orcid.org/0000-0003-3607-213X</orcidid></addata></record> |
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| subjects | Annealing annealing holding time Carrier mobility Circuit design Energy consumption Engineering Engineering, Electrical & Electronic Field effect transistors Grain boundaries Grain size Iron Logic gates Low voltage Metal oxide semiconductors Metal oxides Nanofibers NFs FET Optimization Performance enhancement Performance evaluation Science & Technology Semiconductor devices Technology Threshold voltage Tin dioxide Transistors Transport properties Zinc oxide |
| title | Modulating the Transport Properties of Metal Oxide Nanofibers Transistors by Controlling the Grain Size |
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