Microstructure and Granularity Effects in Electromigration

The persistent advancements made in the scaling and vertical implementation of front-end-of-line transistors has reached a point where the back-end-of-line metallization has become the bottleneck to circuit speed and performance. The continued scaling of metal interconnects at the nanometer scale has shown that their behavior is far from that expected from bulk films, primarily due to the increased influence that the microstructure and granularity plays on the conductive and electromigration behavior. The impact of microstructure is noted by a sharp shift in the changing crystal orientation at the grain boundaries and the roughness introduced at the interfaces between metal films and the surrounding dielectric or insulating layers. These locations are primary scattering centers of conducting electrons, impacting a film's electrical conductivity, but they also impact the diffusion of atoms through the film during electromigration. Therefore, being able to fully understand and model the impact of the microstructure on these phenomena has become increasingly important and challenging, because the boundaries and interfaces must be treated independently from the grain bulk, where continuum simulations become insufficient. In light of this, recent advances in modeling electromigration in nanometer sized copper interconnects are described, which use spatial material parameters to identify the locations of the grain boundaries and material interfaces. This method reproduces the vacancy concentration in thin copper interconnects, while allowing to study the impact of grain size and microstructure on copper interconnect lifetimes.