Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications

Summary This paper presents two low‐voltage high‐speed shallow‐depth current mode logic (CML) topologies. The number of stacked transistors of these proposed structures decreases between VDD to GND. Reduce stacks in proposed gates enhance the circuit to operate at lower supply voltages. Therefore, the proposed logic causes to use of a stand‐alone multiple‐input gate instead of a low‐input gate. The use of decomposing multiple‐input gate for some input series causes error in the output of the circuit. In advanced technologies with size scaling down, the reliability and correctness of data in memories are essential issues. Error correction codes (ECCs) are used for protecting memories against faults. Reducing power consumption with preserving speed is vital in the design of ECCs. The units of ECCs are composed of multiple‐input gates; hence, using a low‐voltage high‐performance structure is required. The essential properties of the proposed logic are low‐voltage and high‐speed operation modes. It also gains in delay improvement of the proposed structure and multiple‐tailed current mode logic (MTCML) than source‐coupled logic (SCL) about 27% and 21% in the low‐voltage design. The final power delay product (PDP) of proposed logic and MTCML is improved by about 14% and 11% than SCL. One‐way to reduce power consumption is by lowering supply voltage in circuits. This paper presents low‐voltage and high‐speed stand‐alone multiple‐input complex gates based on current mode logic topologies. The proposed logic reduces the number of stacked transistors that lead to a decrease in the delay. Proposed logic causes to use of stand‐alone multiple‐input gate instead of a low‐input subnetwork gate. The delay improvement of the proposed structure and multiple‐tailed current mode logic (MTCML) than source‐coupled logic (SCL) is about 27% and 21% in the low‐voltage design.