Co‐design implementation of High Efficiency Video Coding standard encoder on Zynq MPSoC

Summary Statistical analysis of High Efficiency Video Coding (HEVC) encoder reveals that in the motion compensation block, the interpolation filter consumes more than 30% in the encoder time in comparison with other blocks. In this paper, we start with an optimized hardware implementation of the int...

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Veröffentlicht in:	International journal of circuit theory and applications 2021-04, Vol.49 (4), p.1013-1027
Hauptverfasser:	Touzani, Hajar, Mansouri, Anass, Errahimi, Fatima, Ahaitouf, Ali
Format:	Artikel
Sprache:	eng
Schlagworte:	Coders Coding Coding standards Field programmable gate arrays Hardware HEVC HW/SW co‐design Interpolation interpolation filter design Microprocessors Motion compensation Petalinux Power consumption Programmable logic arrays Software Statistical analysis Video compression Zynq SoC
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