Next-generation ferroelectric domain-wall memories: principle and architecture

The downscaling of commercial one-transistor–one capacitor ferroelectric memory cells is limited by the available signal window for the use of a charge integration readout technique. However, the erasable conducting charged walls that occur in insulating ferroelectrics can be used to read the bipolar domain states. Both out-of-plane and in-plane cell configurations are compared for the next sub-10-nm integration of ferroelectric domain wall memories with high reliability. It is highlighted that a nonvolatile read strategy of domain information within mesa-like cells under the application of a strong in-plane read field can enable a massive crossbar connection to reduce mobile charge accumulation at the walls and crosstalk currents from neighboring cells. The memory has extended application in analog data processing and neural networks. In-plane domain wall memory. Cross-bar architecture of three-terminal mesa-like cells with written bipolar domain information (thick arrows) using L and R electrodes, which can be read out at a sufficiently high voltage applied between M and R accompanied by erasure/creation of conductive domain walls (red dotted line).