Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs
In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs...
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| Veröffentlicht in: | IEEE transactions on electron devices 2021-03, Vol.68 (3), p.1352-1357 |
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| container_title | IEEE transactions on electron devices |
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| creator | Lu, Peng Colombeau, Benjamin Hung, Steven Li, Weicong Duan, Xicheng Li, Yifei Bazizi, El Mehdi Natarajan, Sanjay Woo, Jason C. S. |
| description | In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by 4.0\times ( 2.7\times ) and 1.8\times ( 2.1\times ) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs. |
| doi_str_mv | 10.1109/TED.2021.3052432 |
| format | Article |
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S.</creator><creatorcontrib>Lu, Peng ; Colombeau, Benjamin ; Hung, Steven ; Li, Weicong ; Duan, Xicheng ; Li, Yifei ; Bazizi, El Mehdi ; Natarajan, Sanjay ; Woo, Jason C. S.</creatorcontrib><description><![CDATA[In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by <inline-formula> <tex-math notation="LaTeX">4.0\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">2.7\times </tex-math></inline-formula>) and <inline-formula> <tex-math notation="LaTeX">1.8\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">2.1\times </tex-math></inline-formula>) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs.]]></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2021.3052432</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>3-nm node ; CAD ; Computer aided design ; Design optimization ; Doping ; Field effect transistors ; fin field-effect transistor (FinFET) ; FinFETs ; Geometry ; Junctions ; Logic gates ; Modules ; Nodes ; optimization methods ; Performance enhancement ; Performance evaluation ; Semiconductor devices ; Silicon ; source/drain extension (SDE) ; technology computer-aided design (TCAD) simulation ; Variability</subject><ispartof>IEEE transactions on electron devices, 2021-03, Vol.68 (3), p.1352-1357</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-2e98dac2dadeeb3747b69a1fc7ca66983a757f53f8797807b1085d4bd7cd1ca63</citedby><cites>FETCH-LOGICAL-c291t-2e98dac2dadeeb3747b69a1fc7ca66983a757f53f8797807b1085d4bd7cd1ca63</cites><orcidid>0000-0002-2053-6270 ; 0000-0001-8704-7159 ; 0000-0001-9043-6868 ; 0000-0002-7284-8620</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9344635$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9344635$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lu, Peng</creatorcontrib><creatorcontrib>Colombeau, Benjamin</creatorcontrib><creatorcontrib>Hung, Steven</creatorcontrib><creatorcontrib>Li, Weicong</creatorcontrib><creatorcontrib>Duan, Xicheng</creatorcontrib><creatorcontrib>Li, Yifei</creatorcontrib><creatorcontrib>Bazizi, El Mehdi</creatorcontrib><creatorcontrib>Natarajan, Sanjay</creatorcontrib><creatorcontrib>Woo, Jason C. S.</creatorcontrib><title>Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description><![CDATA[In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by <inline-formula> <tex-math notation="LaTeX">4.0\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">2.7\times </tex-math></inline-formula>) and <inline-formula> <tex-math notation="LaTeX">1.8\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">2.1\times </tex-math></inline-formula>) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs.]]></description><subject>3-nm node</subject><subject>CAD</subject><subject>Computer aided design</subject><subject>Design optimization</subject><subject>Doping</subject><subject>Field effect transistors</subject><subject>fin field-effect transistor (FinFET)</subject><subject>FinFETs</subject><subject>Geometry</subject><subject>Junctions</subject><subject>Logic gates</subject><subject>Modules</subject><subject>Nodes</subject><subject>optimization methods</subject><subject>Performance enhancement</subject><subject>Performance evaluation</subject><subject>Semiconductor devices</subject><subject>Silicon</subject><subject>source/drain extension (SDE)</subject><subject>technology computer-aided design (TCAD) simulation</subject><subject>Variability</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kN1LwzAUxYMoOKfvgi8Bn7vlq03zKFunwlBh09eStrczY01r0on7703d8Ol-8Dvncg9Ct5RMKCVqus7mE0YYnXASM8HZGRrROJaRSkRyjkaE0DRSPOWX6Mr7bRgTIdgIfa_avSthOnfaWJz99GC9aS2et52xG5zZjbEAbujr1uEP7YwuzM70B7zad50D_4drW-E3cAFptC0h6D6H2oDtcfDlkW3wS1sBXhi7yNb-Gl3Ueufh5lTH6D2sZ0_R8vXxefawjEqmaB8xUGmlS1bpCqDgUsgiUZrWpSx1kqiUaxnLOuZ1KpVMiSwoSeNKFJUsKxoQPkb3R9_OtV978H2-Df_acDJnQvFYiZSyQJEjVbrWewd13jnTaHfIKcmHdPOQbj6km5_SDZK7o8QAwD-uuBAJj_kvyv125Q</recordid><startdate>20210301</startdate><enddate>20210301</enddate><creator>Lu, Peng</creator><creator>Colombeau, Benjamin</creator><creator>Hung, Steven</creator><creator>Li, Weicong</creator><creator>Duan, Xicheng</creator><creator>Li, Yifei</creator><creator>Bazizi, El Mehdi</creator><creator>Natarajan, Sanjay</creator><creator>Woo, Jason C. S.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-2053-6270</orcidid><orcidid>https://orcid.org/0000-0001-8704-7159</orcidid><orcidid>https://orcid.org/0000-0001-9043-6868</orcidid><orcidid>https://orcid.org/0000-0002-7284-8620</orcidid></search><sort><creationdate>20210301</creationdate><title>Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs</title><author>Lu, Peng ; Colombeau, Benjamin ; Hung, Steven ; Li, Weicong ; Duan, Xicheng ; Li, Yifei ; Bazizi, El Mehdi ; Natarajan, Sanjay ; Woo, Jason C. S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-2e98dac2dadeeb3747b69a1fc7ca66983a757f53f8797807b1085d4bd7cd1ca63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>3-nm node</topic><topic>CAD</topic><topic>Computer aided design</topic><topic>Design optimization</topic><topic>Doping</topic><topic>Field effect transistors</topic><topic>fin field-effect transistor (FinFET)</topic><topic>FinFETs</topic><topic>Geometry</topic><topic>Junctions</topic><topic>Logic gates</topic><topic>Modules</topic><topic>Nodes</topic><topic>optimization methods</topic><topic>Performance enhancement</topic><topic>Performance evaluation</topic><topic>Semiconductor devices</topic><topic>Silicon</topic><topic>source/drain extension (SDE)</topic><topic>technology computer-aided design (TCAD) simulation</topic><topic>Variability</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lu, Peng</creatorcontrib><creatorcontrib>Colombeau, Benjamin</creatorcontrib><creatorcontrib>Hung, Steven</creatorcontrib><creatorcontrib>Li, Weicong</creatorcontrib><creatorcontrib>Duan, Xicheng</creatorcontrib><creatorcontrib>Li, Yifei</creatorcontrib><creatorcontrib>Bazizi, El Mehdi</creatorcontrib><creatorcontrib>Natarajan, Sanjay</creatorcontrib><creatorcontrib>Woo, Jason C. S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lu, Peng</au><au>Colombeau, Benjamin</au><au>Hung, Steven</au><au>Li, Weicong</au><au>Duan, Xicheng</au><au>Li, Yifei</au><au>Bazizi, El Mehdi</au><au>Natarajan, Sanjay</au><au>Woo, Jason C. S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2021-03-01</date><risdate>2021</risdate><volume>68</volume><issue>3</issue><spage>1352</spage><epage>1357</epage><pages>1352-1357</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract><![CDATA[In this article, variability suppression and performance enhancement through source/drain extension (SDE) module engineering is demonstrated in 3-nm node fin field-effect transistors (FinFETs). The process variabilities induced by different modules are systematically quantified in 3-nm node FinFETs using fully calibrated technology computer-aided design (TCAD) tools. With experimentally characterized geometry parameters and their variation ranges, the fin and the SDE module are identified as the main variability sources. The unique device performances induced by the realistic fin and SDE modules are interpreted. Previously developed for performance enhancement in 7- and 10-nm node FinFETs, 3-D SDE doping profile engineering can effectively reduce fin and SDE module-induced variabilities by <inline-formula> <tex-math notation="LaTeX">4.0\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">2.7\times </tex-math></inline-formula>) and <inline-formula> <tex-math notation="LaTeX">1.8\times </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">2.1\times </tex-math></inline-formula>) in 3-nm node n-(p-)FinFETs, respectively. In addition, the precise control of the vertical SDE profile enables a new dimension for design optimization. An optimization methodology for the 3-D SDE doping profile is demonstrated, achieving a 7% (10%) ON-state current enhancement in 3-nm node n-(p-)FinFETs.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2021.3052432</doi><tpages>6</tpages><orcidid>https://orcid.org/0000-0002-2053-6270</orcidid><orcidid>https://orcid.org/0000-0001-8704-7159</orcidid><orcidid>https://orcid.org/0000-0001-9043-6868</orcidid><orcidid>https://orcid.org/0000-0002-7284-8620</orcidid></addata></record> |
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| subjects | 3-nm node CAD Computer aided design Design optimization Doping Field effect transistors fin field-effect transistor (FinFET) FinFETs Geometry Junctions Logic gates Modules Nodes optimization methods Performance enhancement Performance evaluation Semiconductor devices Silicon source/drain extension (SDE) technology computer-aided design (TCAD) simulation Variability |
| title | Source/Drain Extension Doping Engineering for Variability Suppression and Performance Enhancement in 3-nm Node FinFETs |
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