Power-aware hold optimization for ASIC physical synthesis

Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) providers to fix hold timing violations, but there has bee...

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Bibliographische Detailangaben

Veröffentlicht in:	Integration (Amsterdam) 2021-01, Vol.76, p.13-24
Hauptverfasser:	Chentouf, Mohamed, Stevmelin, Foffie, Alaoui Ismaili, Zine El Abidine
Format:	Artikel
Sprache:	eng
Schlagworte:	Application specific integrated circuits Circuit design Design optimization Electronic design automation Energy consumption Energy efficiency Hold timing optimization Index terms— application specific integrated circuits Integrated circuits Physical design Place and route Power consumption Power optimization Setup timing optimization Timing analysis
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