Power-aware hold optimization for ASIC physical synthesis

Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) providers to fix hold timing violations, but there has been no effort to study the impact of each technique on power consumption. Nowadays, the rise of low power applications demand keeps pushing for the invention of new power reduction techniques. In this paper, we presented a novel approach for power consumption reduction by reducing the power increase seen during the hold timing optimization. A sample of 100 industrial post-CTS designs from different applications and fabrication process technologies (from 180 nm to 28 nm) was used to measure the ratios of Δpower/Δhold_timing and Δarea/Δhold_timing of each technique. The ratios were calculated after legalization and global routing to include not only the power/area added directly by the hold optimization, but also the power/area increases induced indirectly by the additional timing fixes needed after placement legalization and routing repair. By considering the impact on power consumption and area increase of each technique while optimizing the design we have reduced substantially the power increase and the area overhead caused by the hold fixing. Experimental results show a power reduction of 7%, and an area reduction of 1% on average, with a beneficial impact on hold timing and a neutral impact on setup timing.